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Altera_Forum
Honored Contributor I
1,024 Views

set design clock

Hi All, 

 

I have hard time trying to create clock based process in Verilog. I am using mini board with EP2C5T144C8 chip. I rote a simple code ad checking 

output signals with scope. I assign clock pin to pin 17 according to schematic this is where 50 Mhz osc connected to. But I don't see any signals on scope. 

 

What I am doing wrong? 

 

 

 

 

 

 

 

module encoder (CLK,enc_out); 

input CLK; 

 

output enc_out; 

reg enc_out; 

 

integer cnt = 0; 

 

 

always @(posedge CLK) 

begin 

 

cnt = cnt+1; 

if(cnt<25000) enc_out = 1; 

else enc_out = 0; 

if(cnt==50000) cnt = 0; 

 

end 

 

endmodule
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5 Replies
Altera_Forum
Honored Contributor I
18 Views

Do not use integer type. Use a register instead.  

reg [15:0] cnt; 

then in the clock process you must make some changes, like: 

cnt <= cnt + 16'd1;
Altera_Forum
Honored Contributor I
18 Views

Thank Cris72, 

 

I tryed this and it doesn't help. Its even worse. 

 

this code is working - I see on scope enc_out following end_inp: 

 

always @(enc_inp)//posedge CLK) 

begin 

enc_out<=enc_inp; 

 

end  

 

but this one not: 

always @(posedge CLK) 

begin 

enc_out<=enc_inp; 

 

end 

 

 

I am lost....
Altera_Forum
Honored Contributor I
18 Views

You definitely have no CLK signal. 

Probably you have a bad pin assignment.
Altera_Forum
Honored Contributor I
18 Views

Why the 2nd always block works is coz, its no longer a clocked sequential block, but a combinational block. The output follows the input whenever there's a change in the input. 

Try with a clock and reset, and also as Cris72 mentioned, check Pin assignments, use [15:0] instead of integers. Try the following code and check: 

 

module encoder ( clock, reset, // Its good to use a reset so that Flops are set to a known state. enc_out ); input clock; input reset; output enc_out; reg enc_out; reg count; always @(posedge clock or negedge reset) begin if(!reset) begin count <= 16'd0; end else begin count <= count + 16'd1; end end always @ (count) begin if (count ==16'd50000) enc_out <= 1'b0; else if (count < 16'd25000) enc_out <= 1'b1; else enc_out <= 1'b0; end endmodule
Altera_Forum
Honored Contributor I
18 Views

Cris72 ya - its look like I don't have right pin assignment. I checked schematic of board and find 50Mhz osc that going into pin17. So I assign pin clock pin 17. but its look like this is still wrong. I will try to find better documentation for this board. 

I tried to find 50Mhz signal on pin directly with scope, but no luck. I don't understand why. 

 

eapenabrm thx for help, but 

why you are using not decimal numbers like cnt = 25000; but cnt = 16'd25000 does it matter?
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