set_false_path -fall

Altera_Forum · ‎05-08-2011

I have an asynchronous reset_n (active low) signal.

It goes through a couple of flops to result in an asynchronous assertion, synchronous de-assertion signal. Something like this: assign pclk_reset_n = pclk_reset_n_dd & reset_n;

I want to ignore the timing of the falling edge of pclk_reset_n, but I do want timing analyzed on the rising edge of pclk_reset_n, but I'm not sure how to write the constraint...

I would have thought I could use something like (with -fall):

set_false_path -fall -from reset_n

but I don't see it listed in the Altera SDC manual.

Any suggestions?

Thanks,

Torrey

Altera_Forum · ‎05-08-2011

You don't need to.

TimeQuest checks recovery/removal of involved registers at reset deassertion only