set false path if over some logic levels

[Altera_Forum]

hi, I want to set a false path on all paths having more than some no. of levels. 

we are porting an asic design and this arises when certain modules are instantiated together. The resulting paths are clearly false and I don't have a simple means of identifying using -from or -to commands. Only good indicator is the number of levels or length of path. thanks,

[Altera_Forum]

There isn't any easy command that dumps the levels of logic. You can get timing reports and go through each one and get that info, but it would be very time consuming, and would require a complex flow(synthesize, do timing analysis and find all the long paths, create an .sdc, then run the fitter...) 

FYI, levels of logic is not a good indicator in FPGA's because they can vary so much. For example, I see paths with 16-32 levels of logic that run very fast, but that's because they're in a carry chain. Conversly, I see single levels of logic that are a memory with no output registers, and hence a large access time that would probably equal a few levels of logic in LUTs. On top of that, there's a lot of variance. There are some paths through a LUT that are extremely fast, and some that are very slow. Adding it all up, it makes "levels of logic" a measure that isn't overly useful. (When looking at a path, one can quickly see these things and understand them, so we still report the levels of logic, I'm just saying it hasn't been pursued as a means for identifying things.)  Can you do the opposite and just look for large failures? That comes out of report_timing much easier, and I assume is a similar issue?

[Altera_Forum]

Hi Rysc, yes I can check for large failures. But how can I turn this into 

a false path like constraint? Iwant to say something to the STA that if you see violations like -100ns or more, ignore them as they are false.

[Altera_Forum]

I'm sure there are ways to script it, which if the design is changing, you might want to do. If it's a one-time process, I would just run something like: 

report_timing -setup -npaths 5000 -detail pairs_only -panel_name "long list" (You can filter the clock or node names with -from/-to or -from_clock/-to_clock) You now have a long list at the top. You could copy and paste that into .xls which is pre-filled with set_false_path and -from and -to columns. Then just paste these columns of names in between. Then just copy the whole thing into your .sdc.  Note that you can just Reset Design in TimeQuest. It will then read in your new .sdc, and when you run report_timing it will show the analysis with the new constraints, so you can iteratively find them and make sure you get them all, without re-fitting each time. I'm not a fan of having thousands of individual set_false_path commands, so if you can do any wildcarding, that might help run-times.