Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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set_max_delay and set_min_delay is no sense for project compile

lambert_yu
Beginner
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Hi sir,

     I face one problem, and I have no idea for the set_max_delay and set_min_delay constrains, the problem as follows:

     I want to constrains the delay from the reg_q to the port_o, but I found there is no effect when I constrain the datapath, and the time report presents the delay is large the value that I set.

   The timing report as follows:

     

 

     the constrains as follows:

     set_min_delay  -from spi_master_wrap_u|spi_tx_u|tx_sck_o|q -through spi_master_wrap_u|sck_o~0|combout -to m_spi_ck_o~output|i 0.200

     set_max_delay  -from spi_master_wrap_u|spi_tx_u|tx_sck_o|q -through spi_master_wrap_u|sck_o~0|combout -to m_spi_ck_o~output|i 2.100

     Is there any problem for the constarins or it's not correct to use these constrains. Would someone will help me?

  Software:quartus II 13.1 

  FPGA chip: Arria V AGXA7

Best regards,

Lambert

 

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6 Replies
KhaiChein_Y_Intel
683 Views

Hi,


This might due to the value you set exceeds the limitation of the max/min delay value.


Thanks

Best regards,

KhaiY


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lambert_yu
Beginner
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Hi KhaiY

   I am  so happy for your response, but would you help me to know how can I estimate or find the limitation for the max/min delay value?

 

Best regards,

Lambert

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KhaiChein_Y_Intel
670 Views

Hi,


It depends on the location of the source and destination. If you set min/max delay and you see the delay in the Timing Analyzer exceeds the value that you set, the value in the Timing Analyzer is min/max for the same source/destination location.


Thanks

Best regards,

KhaiY


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lambert_yu
Beginner
669 Views

Hi KhaiY,

   If so, I want to know, if the max/min value which I set is not satisfied by software, will it provide violation message? Now, it does not present this message in timing report, it's normal?

 

BR,

Lambert

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KhaiChein_Y_Intel
659 Views

Hi Lambert,


You are correct. This will not reported as warning or error message.


Thanks

Best regards,

KhaiY


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KhaiChein_Y_Intel
645 Views

Hi,


We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


Best regards,

KhaiY


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