I face one problem, and I have no idea for the set_max_delay and set_min_delay constrains, the problem as follows:
I want to constrains the delay from the reg_q to the port_o, but I found there is no effect when I constrain the datapath, and the time report presents the delay is large the value that I set.
The timing report as follows:
the constrains as follows:
set_min_delay -from spi_master_wrap_u|spi_tx_u|tx_sck_o|q -through spi_master_wrap_u|sck_o~0|combout -to m_spi_ck_o~output|i 0.200
set_max_delay -from spi_master_wrap_u|spi_tx_u|tx_sck_o|q -through spi_master_wrap_u|sck_o~0|combout -to m_spi_ck_o~output|i 2.100
Is there any problem for the constarins or it's not correct to use these constrains. Would someone will help me?
Software:quartus II 13.1
FPGA chip: Arria V AGXA7
It depends on the location of the source and destination. If you set min/max delay and you see the delay in the Timing Analyzer exceeds the value that you set, the value in the Timing Analyzer is min/max for the same source/destination location.
If so, I want to know, if the max/min value which I set is not satisfied by software, will it provide violation message? Now, it does not present this message in timing report, it's normal?
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