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Altera_Forum
Honored Contributor I
1,678 Views

set_max_skew constraint

I have a video bus, consisting of DATA, SYNC and CLOCK_OUT. DATA and SYNC are latched by an external receiver at the falling edge. As it has symmetrical (and long) setup and hold requirements I clock DATA and SYNC out with the rising edge. Including the variation in clock symmetry I must deliver DATA and SYNC with +/- 5.5ns in relation to CLOCK_OUT. Clock source comes via a pin and I use these global clock both for clocking the DATA and SYNC registers and for generating the CLOCK_OUT (CLOCK_OUT <= CLK_IN). 

 

I added the constraint 

set_max_skew -from { CLOCK_OUT} -to [get_ports {DATA*}] 5.4 

 

but I get the warning :( 

 

Warning: No path is found satisfying assignment "set_max_skew -from [get_keepers { CLOCK_OUT }] -to [get_ports {DATA*}] 5.400 ". This assignment will be ignored. 

 

Hope to get again the excellent support....
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5 Replies
Altera_Forum
Honored Contributor I
100 Views

This isn't really a skew scenario. (Skew is for comparing all combinations of the signals, where really you want the data/sync compared to the clock). What's the clock period?

Altera_Forum
Honored Contributor I
100 Views

Argh. Typed something up and it didn't get submitted. Here we go again... 

Let's assume the clock is 20ns 

 

create_clock -period 20.0 -name clk_in [get_ports {clk_in}] 

derive_pll_clocks ;# out of habit 

derive_clock_uncertainty 

 

create_generated_clock -invert -name clk_out_ext -source [get_ports clk_in] [get_ports clk_out] 

 

set_output_delay -clock clk_out_ext -max 4.6 [get_ports {data[*]}] 

set_output_delay -clock clk_out_ext -min -4.6 [get_ports {data[*]}] 

 

- The generated clock says a clock based on clk_in goes out clk_out. The invert option says it is inverted at the external device(the -invert does nothing to the clock inside the FPGA). 

- Since the FPGA clock is not inverted but the external one is, you will have a setup relationship of 10ns and hold relationship of -10ns. That means across the interface, the data can be skewed by +/-10ns compared to the clock. 

- The set_output_delays are saying that externally there is +/-4.6ns of skew being added. Since the interface allows +/-10, that leaves the FPGA with +/-5.4ns.
Altera_Forum
Honored Contributor I
100 Views

OK I understand (it needs some time to convert from classic analyzer to Timequest) 

 

In line 

create_generated_clock -invert -name clk_out_ext -source [get_ports clk_in] [get_ports clk_out] 

you have two clocks, the incoming clk_in and outgoing clk_out. Is this a mistake? I think, if not, the master_clock option is missing. If J just write it down in this manner, the first is taken. 

Anyway, as far as I understand TimeQuest's calulation it always takes the incoming clk_in for calculating output_delay. As my external latching circuit sees clk_out as sample clock and this clock has a routing delay to clk_in, can I take this into account? That makes life more easy as I then have delays in both data and clock paths.
Altera_Forum
Honored Contributor I
100 Views

You mean two ports? The first one is tied to the option -source, saying physically where the clock is coming from, and then clock constraint is applied to the last one. (.sdc constraints like create_clock and create_generated_clock have a target they are applied to, which is implied, i.e. it's the one with no option. I wish it was more explicit too.) 

This generated clock is necessary to show how clk_in get off chip(by the output port clk_out).  

The routing delay to clk_in doesn't really matter, as it affects both the data and clk_out going off chip equally. You can account for different board delays between the FPGA and external latching device. Basically any board delay on the data output to external device is added to the output delay and any board delay for the clk_out to external device is subtracted.
Altera_Forum
Honored Contributor I
100 Views

Hi, 

I've understood, all is working fine (had a look at the various delay chains). Thanks a lot :)
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