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Hello people!
I am kind of new to VHDL and I was wondering when one can use the X'last_value for a signal and when does that have a meaningful value. I mean except for the use with the clock signal, i do not know how the FPGA keeps track of the previous values of every signal.
For example I have a clocked process that has only the clock and reset at its sensitivity list. Inside the rising_edge block of the process i need to check the previous value of a signal that changes in a much slower pace than my clock. My main question is:
Is the "system" saving the previous value of every signal that is registered with this clock in every clock cycle?
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No there is no such thing as automatic memory of signal values. The expression you mentioned is just the way the compiler used to understand clock signal for registers. I normally use if rising_edge(clk) ... i.e. function format
