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Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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signal tap error

Altera_Forum
Honored Contributor II
‎05-14-2013 05:31 AM
1,127 Views

i am getting the below error, how to resolve? 

Error: Port "pre_syn.bp.UI_PM_CNTROLER_VALID_SPI" does not exist in the interface of the partition "F1_PM_HANDLER:PM_HANDLER_INST", but another partition attempted to connect to it
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Altera_Forum
Honored Contributor II
‎05-17-2013 08:22 AM
395 Views

Any news about your problem? 

 

Is this signal listed in SignalTap? If yes, I suppose, it is read. Why don't you delete that signal and choose another one?
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