signed input signal does not show "signed" in .vo

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hi,everyone: 

I edited a program about CORDIC,but I got a problem.  I declared some "signed input" in .v file. But after synthesizing,signed  input does not show "signed" in .vo file.That causes some warning  message such as"# RUNTIME: Warning: RUNTIME_0154 cycloneii_atoms.v  (6702): Replication multiplier is not positive: 0 "when I operate timing  simulation with Active HDL8.1. And the output signal values of timing  simulation are not the same as those of funtional simulation. How can I solve this problem?    I use Quartus 7.2sp3,cyclone II EP2C35F672C6 and Active HDL8.1. AND I listed .v and .vo file below:   1. Shift_adder_subtractor.v:  module Shift_adder_subtractor ( X ,Y ,i ,A ,B ,Sign_X_mul_Y ,u ,m,clk,rst,out_en);    input [4:0]i ;  wire [4:0]i ;  input signed[17:0] A ;  wire signed[17:0] A ;  input signed[17:0] B ;  wire signed[17:0] B ;  input signed [1:0]u ;  wire signed [1:0]u ;  input signed [1:0]m ;  wire signed [1:0]m ;  input clk ;  wire clk ;  input rst ;  wire rst ;  output out_en ;  reg out_en ;  output signed[17:0] X ;  reg signed[17:0] X ;  output signed[17:0] Y ;  reg [17:0] Y ;  output signed [1:0]Sign_X_mul_Y ;  reg signed [1:0]Sign_X_mul_Y ;    reg signed[17:0] A1;  reg signed[17:0] B1 ;  reg[2:0]state;  `define idle 0   `define shift_A_B 1  `define sel_sys_mode 2  `define add_subtract 3  `define out_X_Y 4   //}} End of automatically maintained section    // -- Enter your statements here -- //      always @(posedge clk or negedge rst)    begin   if(!rst)  begin  out_en<=1'b0;   A1<=18'sh0;  B1<=18'sh0;  Sign_X_mul_Y<=2'sb1;  X<=18'sh0;  Y<=18'sh0;  state<=`shift_A_B;  end  else  begin   //if(en==1'b1) state<=`shift_A_B;  //else state<=`idle;  case(state)  `idle:  begin   state<=`shift_A_B;  end  `shift_A_B:  begin  out_en<=1'b0;  A1<=A>>>i;  B1<=B>>>i;  state<=`sel_sys_mode;  end  `sel_sys_mode:  begin  A1<=u*A1;  B1<=m*u*B1;  state<=`add_subtract;  end  `add_subtract:  begin  A1<=A-B1;  B1<=A1+B;  state<=`out_X_Y;  end   `out_X_Y:  begin  Sign_X_mul_Y<={A1[17]|B1[17],1'b1};  X<=A1;  Y<=B1;  state<=`idle;  out_en<=1'b1;  end  endcase  end   end    endmodule 2.Shift_adder_subtractor .vo:   timescale 1 ps/ 1 ps module Shift_adder_subtractor (  X,  Y,  i,  A,  B,  Sign_X_mul_Y,  u,  m,  clk,  rst,  out_en); output [17:0] X; output [17:0] Y; input [4:0] i; input [17:0] A; input [17:0] B; output [1:0] Sign_X_mul_Y; input [1:0] u; input [1:0] m; input clk; input rst; output out_en; ......