simulate a vhdl code of a function with ISE

[Altera_Forum]

I've started to learn vhdl recently.i write a vhdl code to detemine the arith  

statement,but it dosen't work.actually when i simulate it;the output dose not  change and it remains 0.0; i don't know where is my mistake.Do I need to use a  external clock??i do it but it dose not change :-( please help me   library IEEE; use IEEE.STD_LOGIC_1164.ALL; package mypack is type real_vector is array (integer range <>) of real; end mypack; library IEEE; use IEEE.STD_LOGIC_1164.ALL; --use IEEE.STD_LOGIC_UNSIGNED.ALL; use work.mypack.all;  entity convolution is port (x:in real_vector(0 to 3);  y:in real_vector(0 to 1);    f:out real_vector (0 to 4)); end convolution; architecture Behavioral of convolution is --signal temp : real_vector (0 to 4):= (others => 0.0); --signal enable : std_logic :='0'; begin process (x,y) variable sum :real; begin  for n in f'range loop  enable <= '0';  for k in y'range loop  sum:=sum + x(k)*y(n-k);  end loop;  -- temp(n) <= sum;  f(n) <= sum ;  sum:=0.0;  end loop; enable <= '1'; --if (enable'event and enable='1') then -- f <= temp; --end if; end process;   end Behavioral;

[Altera_Forum]

I'm nut even sure how this code can run in a simulator without any errors but you should maybe check your algorithm first. In this linesum:=sum + x(k)*y(n-k);(n-k) can take a lot of values outside of the range 0 to 1, and that should cause an error in the simulator real quick. 

You do realize that this code isn't synthesizable on real hardware, don't you?

[Altera_Forum]

--- Quote Start ---  I'm nut even sure how this code can run in a simulator without any errors but you should maybe check your algorithm first. In this linesum:=sum + x(k)*y(n-k);(n-k) can take a lot of values outside of the range 0 to 1, and that should cause an error in the simulator real quick. You do realize that this code isn't synthesizable on real hardware, don't you?  --- Quote End ---    thank you for your reply actually i want to simulate an upsampler (in DSP); and for implemet this ,i need to implement a convolution function,therfore i used that vhdl code(that is sent) and that is wrong. i don't know how can do it;please help me thank you  hello,i changed my vhdl to the following code,but the output remains 0 and dosen't change when the inputs change,where is my mistake?? package mypack is type real_vec is array(integer range <> ) of real; end mypack; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use work.mypack.all; entity conv1 is generic (m:integer :=3;  n:integer :=1); port (x:in real_vec(0 to m);  y:in real_vec(0 to n);  f:out real_vec(0 to m+n)); end conv1; architecture Behavioral of conv1 is signal h : real_vec(-(m+n) to m+n):=(others =>0.0); --signal h : real_vec(-m to n):=(others =>0.0); signal sum:real:=0.0; begin process (x,y) begin h(0 to n) <=y; for i in 0 to m+n loop    for k in 0 to m loop  sum <= sum + x(k)* h(i-k);  end loop;  f(i) <= sum;  sum <=0.0; end loop; end process;  end Behavioral;

[Altera_Forum]

In this linesum <= sum + x(k)* h(i-k);as sum is a signal, it will only get its value from the simulator after the process was executed. There is always asmall delay (called delta delay) before a signal gets it's value. Therefore sum will always stay at 0. If you want to make an accumulator that is updated without waiting between each operation, you need to make sum a variable. 

But this still isn't synthesizable, as you are using reals. Even if it where, as you are doing all the operations simultaneously it will generate a very complicated hardware as you increase the values of n and m. I would suggest to use fixed point types instead of reals, and add a clock to do only one multiplication/accumulation per clock cycle.