Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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simulation waveform for more than 1micro second

Altera_Forum
Honored Contributor II
5,183 Views

Hi, 

I am using Quartus 2 version 9. I need to simulate my VHDL code (vector waveform file) for few seconds. However the quartus 2 simulates only upto 1 micro second. 

Does anyone know how to increase the simulation time. 

 

Thanks in advance.
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Altera_Forum
Honored Contributor II
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Hello! 

 

Open the waveform file and go to "Edit -> End Time..." 

There you can increase the total time of your simulation 

 

Regards, 

Thiago
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Altera_Forum
Honored Contributor II
3,163 Views

Yes You can increase up to 100us, but if you need to longer time it says that max time is 100us. is there a possibility to increase more than 100us?

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Altera_Forum
Honored Contributor II
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I'm using Quartus II v9.1 SP2 and apparently it has no problems setting longer simulation periods. I was even able to set the end time to 1000s.  

Which version are you using?
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YMano1
Beginner
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Hey there, I'm having the same issue is the OP (original poster). I want to simulate a few seconds, let's say 10. For the record, I'm also using 9.1 service pack 2.

 

Have you tried actually simulating with an End Time of more than 100 microsecs? Any longer period of time and Quartus will not end the simulation at all.

Will appreciate any help. Thank you!

 

P.S. Regarding why I'm not updating to ModelSim-Altera Starter edition - the reason is, I'm taking this as part of a university course and the version above (9.1p2) is what is on our computers.

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Altera_Forum
Honored Contributor II
3,163 Views

using version 13.1

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Altera_Forum
Honored Contributor II
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Didn't the Quartus Simulator Tool get discontinued on version 10 and above? It has been replaced by the ModelSim-Altera Starter edition if I'm not wrong

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Altera_Forum
Honored Contributor II
3,163 Views

It has made a re-appearance. It only simulates the gate level netlist. It has very limited functionality (input only from VWF files afaik). 

 

So much better to make the transition over to proper simulator, like most of the rest of the engineering community.
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