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Hi all,
When simulating a basic counter (74161) I get spikes in modelsim – but I am unable to zoom in on those spikes in the wave window – see attachment. When analyzing the signals I see that the spikes originates from combinations of signals; such as: SYNTHESIZED_WIRE_22 <= SYNTHESIZED_WIRE_26 XOR SYNTHESIZED_WIRE_41 where the inbound signals SYNTHESIZED_WIRE_26 and SYNTHESIZED_WIRE_41 does not exhibit spikes; but change state at the same instance. This phenomena occurs across many of the signals being combined. Code attached for the simple counter circuit and its "wiring". Any experience to share is highly appreciated. Br /mattiasLink Copied
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A timing simulation? You should see spikes when looking at combinatorial nodes. As long as you've met timing, they all settle before the next clock edge.
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The spikes are normal. The are likely an artifact of wait-statements, eg., "wait for 0 ns".
Modelsim has a list window that shows you a text version of the wave window, you could probably look at that if you really wanted to know more. The main thing to take away from the display is that the signal with glitches is a *combinatorial* signal. Depending on what your design does with that signal, using it as a combinatorial input might be fine, other times you might need to register it, and use the register output. Cheers, Dave- Mark as New
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Thank you both for the input. I feel safe now in progressing.
br /mattias
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