splitting an output bus on a symbol

[Altera_Forum]

Good morning, 

 This is for a project for school and I'm pulling my hair out trying to figure out why I have no sign on life on my board. I have all components working individually (verified using simulation), but put together, I can't get my board to do anything. I suspect my counter connected to the main part of the program is the problem, but I'm not sure how to separate the bus into its individual outputs to test this theory.  This is what I currently have:  http://www.alteraforum.com/forum/attachment.php?attachmentid=13002&stc=1   I'd like to split that bus into q0, q1, and q2 so as to trigger TIMR on only q2. While I can't think of why my strategy above is not working, I'd like to break it down even further. I built the symbol using a VHDL file.  Thank you for taking the time!

[Altera_Forum]

That screenshot of the schematic should be doing exactly what you described. So when the most significant bit of q (bit offset 2) is high then the TIMR input of instance 'lights' will also be driven high. If you wanted to feed the two LSBs of q (bit offsets 0 and 1) to some other block you would use the same technique of labeling a signal wire with the alias q[0] or q[1], or q[1..0] if you wanted to feed those into a 2-bit bus connection. 

 I suspect the wiring is fine and something else is causing the problem. If you are synthesizing this logic and want to see how it's behaving you could wire q[2] out to a pin and look at it with a oscilloscope or signaltap it to see if it's asserted when you expect it to be. I suspect you have a modulo 5 counter driving q[2..0] so I would expect that to behave by driving q[2] high for a single clock cycle, every 5 clock cycles. If that's not what you are suspecting then that is most likely the issue. Also double check what's driving the reset port of that mod5 instance to make sure it's only being reset when you expect it to.

[Altera_Forum]

Thanks for the reply! 

 I think you're right that the connections aren't the trouble. I removed the mod-5 counter and connected lights directly into the frequency divider and still got nothing. teI have a frequency divider going into that mod 5 counter. TIMR should be high every 5 cycles and then go back to low on the next clock cycle. As I typed that out, I need to check that my code actually has TIMR set low on the next clock cycle, otherwise it just stays high forever. That might actually be the problem.  Sometimes it helps to just talk it out! And thank you for suggesting the scope! I was wondering how to sort out waves without a simulation. That works brilliantly!

[Altera_Forum]

Well BadOmen, you were right. It was the reset pins. I completely forgot that my board's buttons are active low. So much stress for something so silly. 

 Thanks again :)