state machine problem

[Altera_Forum]

I create a vhdl program that is a state machine, it compile, but in the vector waveform i cant see my actual state (pr_state) and my next state (nx_state), i dont know what to do, please i need help :( 

this is the vhdl code:   Library ieee; use ieee.std_logic_1164.all; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; --------------------------------------- ENTITY maquinaest IS PORT ( clock,reset:in STD_LOGIC;  S:STD_LOGIC_VECTOR(1 DOWNTO 0);  v: out STD_LOGIC); END maquinaest; ---------------------------------------   ARCHITECTURE secuencial of maquinaest IS type state is (e_0, e_1); signal pr_state: state; signal nx_state: state; BEGIN ---------------LOWER SECTION:--------------------------   PROCESS(reset, clock) BEGIN  IF(reset='1')THEN  pr_state<=e_0;  ELSIF(clock'EVENT AND clock='1') THEN  pr_state<=e_1;  END IF; END PROCESS; ---------------UPPER SECTION:--------------------------  PROCESS(S,pr_state) BEGIN  CASE pr_state IS  WHEN e_0 =>  IF(S="00")THEN  v<='1';  nx_state<=e_1;  END IF;    IF(S="01")THEN  v<='0';  nx_state<=e_0;  END IF;    IF(S="11")THEN  v<='0';  nx_state<=e_0;  END IF;    WHEN e_1 =>  IF(S="11")THEN  v<='0';  nx_state<=e_0;  END IF;     IF(S="01")THEN  v<='1';  nx_state<=e_1;  END IF;     IF(S="00")THEN  v<='1';  nx_state<=e_1;  END IF;     END CASE;  END PROCESS;  END secuencial;

[Altera_Forum]

Hi, 

I think the problem is, that in the "LOWER SECTION" you assign either e_0 to pr_state or (for no reset condition) permanently e_1. The output "v" is based on pr_state and while assigning different values to nx_state in the Upper Section, this change of "nx_State" has no effect on pr_State. Therefore the compiler optimizes an may reduce your state machine to some "simple registered logic"... In short words: I think the failure is located in the lower section, the assignment for the "non reset" path should write   ELSIF(clock'EVENT AND clock='1') THEN pr_state<=nx_state;  Give it a try...  Carlhermann

[Altera_Forum]

man thanks for your help i did what you say, and now appear pr_state and nx_state, but its strange, i cant recognize the states e_o and e_1 in the waveform file. Look , i know that in the waveform pr_state and nx_state look different and they when you simulate should show the states. 

 Look, this is my actual waveformr with your modification:

[Altera_Forum]

Hi, 

I think you see the binary coding of the states, in fact, as there are only two states (e_0 and e_1) coding is just by one single bit "0" and "1". Remove these two nodes from the waveformeditor and try to insert them separately to get them inserted as states, showin e_0 and e_1 rather the binary coding. Inserting state nodes with "normal" nodes ends in sae binary coding representation for my desings as you showed.

[Altera_Forum]

how can i do that? please tell me the steps, dont know how to do it ... thanks for all

[Altera_Forum]

Hi, 

this should not be the problem. Just edit your waveform file as you did for the simulation you ran:  - delete both nodes pr_state and nx_state - insert node => select only pr_state and nx_state (no "not state type" nodes) - this should change the "Type" to Machine and "Value Type" to "Enum" - insert the node(s) and your next simulation should show the states...  Hope that helps, Carlhermann

[Altera_Forum]

i deleted pr_state and nx_state, but i dont understand what you said:insert node => select only pr_state and nx_state (no "not state type" nodes) 

what do you mean when you say "(no "not state type" nodes)" because i find again pr_state and nx_state on node finder... and the program put them in buried, 9-level....

[Altera_Forum]

if i put manually pr_state and nx_state in ype:machine and Value Type: enum. The program makes me this error: 

 Warning: Wrong node type and/or width for node "|maquinaest|pr_state" in vector source file. Node in design is of type 9-Level and of width 1, but node in vector source file is of type Enum and of width 1. Error: Can't simulate mismatched node types Warning: Wrong node type and/or width for node "|maquinaest|nx_state" in vector source file. Node in design is of type 9-Level and of width 1, but node in vector source file is of type Enum and of width 1. Error: Can't simulate mismatched node types Error: Quartus II Simulator was unsuccessful. 2 errors, 2 warnings

[Altera_Forum]

please i need your help!!!

[Altera_Forum]

The Quartus simulator can display internal signals only according to their actual encoding, not in an arbitrary representation as e.g. ModelSim can. 

 In your above waveform, pr_state and mx_state are clearly shown, but you apparently didn't understand the signal representation. Normally, a state machine is encoded as one state hot. In this case, you have to display the register signals assigned to each state as Carlhermann suggested. But in your case, there is only one register bit, which is either '0' or '1'. It can't be displayed different in Quartus simulator, you only have to understand it's meaning. In my opinion, it's simple and straightforward.

[Altera_Forum]

ok, thanks FvM...