std_logic_vector type does not match integer literal

[Altera_Forum]

Error (10517): VHDL type mismatch error at Transmit2.vhd(118): std_logic_vector type does not match integer literal 

 at  constant preamble : STD_LOGIC_VECTOR (31 DOWNTO 0) := 16#55#; -- 16 bits * 2 = 32

[Altera_Forum]

--- Quote Start ---  std_logic_vector type does not match integer literal  --- Quote End ---   That's true according to VHDL specification. Unless you apply a type conversion, std_logic_vector can be only assigned to a bit string literal of correct bit length, e.g.   constant preamble : STD_LOGIC_VECTOR (31 DOWNTO 0) := x"00000055";

[Altera_Forum]

success 

 For hex number 16## <- this wrong x"" <- this correct

[Altera_Forum]

x"012345" is a hex string. It is not an integer.

[Altera_Forum]

i got it, so that i write for hex number, in the another post, i thought it as an integer