Hi ,
i have a digital card with FPGA and i transmit serial data from the FPGA from this card to other external loopback card(connected together)
and then the data back to the the FPGA .
The problem is that the data have variant delay at the digital line and it cause meta stable issue to the signal .
i can't transmit the clk with the data because of technical issue and can't measure the delay line and insert the delay into SDC file because of system request .
which solution can solve this problem ?
