synthesis problem when read a memory content

[Altera_Forum]

if ((Block_Y[0]>=29)  

|| ((Block_Y[0]+Block_Y[1])>=29)   || ((Block_Y[0]+Block_Y[2])>=29)  || ((Block_Y[0]+Block_Y[3])>=29)  || (WritePermit==1)   || (mem[{Block_X[0],(Block_Y[0]+5'b00001)}]==1)  || (mem[{(Block_X[0]+Block_X[1]),(Block_Y[0]+Block_Y[1]+6'b000001)}]==1)  || (mem[{(Block_X[0]+Block_X[2]),(Block_Y[0]+Block_Y[2]+6'b000001)}]==1)  || (mem[{(Block_X[0]+Block_X[3]),(Block_Y[0]+Block_Y[3]+6'b000001)}]==1))  Hi, i am a new user of a FPGA board which has Cyclone II. and my design software is Quartus II 13.0. I want include the above statement in my code(write in verilog), there is no error of the synthesis, but it seems the synthesis result is not what i want. Any suggestion? Thank you.

[Altera_Forum]

You want us to guess what's not working as intended? Obviously it can't infer RAM. Can you guess why? 

 To give a hint, embedded RAM can only access one memory location at a time (in one clock cycle), maximum two if utilizing the dual-port feature.

[Altera_Forum]

--- Quote Start ---  You want us to guess what's not working as intended? Obviously it can't infer RAM. Can you guess why?  To give a hint, embedded RAM can only access one memory location at a time (in one clock cycle), maximum two if utilizing the dual-port feature.  --- Quote End ---     Thank for your reply. You are right. I think I am still not get used to HDL. So can I use a "case" statement and include the above mem[] respectively? Will that synthesis correctly? Thank you.

[Altera_Forum]

Depends on. The shown expression tries to read four different memory locations at once, I presume under the control of an edge sensitive always block. 

 If you write a similar construct in a C program, the compiler reads the memory sequentially. But HDL is a hardware descriptions language, the design compiler synthesizes a hardware that can perform the requested action in one clock cycle. Because it's imposssible in FPGA block RAM, the memory structure will be built in register cells.  The only chance to implement the intended operation in a RAM compatible way is to serialize it, reading one or maximal two (utilizing the said dual-port RAM feature) memory locations per clock cycle. It's unlikely that a simple case strcuture as such will achieve it, you have to organize a sequential access, e.g. using a state machine.   In other words, there's no simple general solution. It depends on the problem and probably involves restructuring of the data processing.

[Altera_Forum]

Thank you so much. I learn a lot from your explanation. It is a bit triky that the coding style of HDL is very important becase it relates to the hardware.  

I will try to use a state machine, like  always(posedge CLK) begin ..... end  always(*) begin case() ... put mem[] in four cases here ... endcase end  I hope it will work. By the way, do we need to initial the memory to all 0 to avoid potential problems?