terASIC data conversion timing

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terASIC data conversion timing

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I am getting some artifacts on one channel of the DAC output on the terASIC Data Conversion card on the Cyclone III development board. I have not set any timing constraints and I am running the DAC clock at 125MHz, so this might be an issue.

The datasheet for the TI DAC5672, the DAC on the data conversion card, lists setup and hold times of 1n.

I'm trying to use the Timing Quest analyzer but I am a little lost as to what I need to do.

I figure that I need to designate the clocking signal as a clock, and indeed it is present in the "Clocks Summary" page. The Wizard has sections for setting t_pd, t_co, t_su, t_h, but I don't see these corresponding sections outside the Wizard -- I looked in the Output Delay area.

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