I have write a code in vhdl for d flip flop as below:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity d_ff_en is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
en : in STD_LOGIC;
d : in STD_LOGIC;
q : out STD_LOGIC);
end d_ff_en;
architecture Behavioral of d_ff_en is
begin
process(clk,reset)
begin
if(reset='1') then
q<='0';
elsif(clk' event and clk='1') then
if (en='1') then
q<=d;
end if;
end if;
end process;
end Behavioral;
and the test bench code is as below:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY dff1_tb IS
END dff1_tb;
ARCHITECTURE behavior OF dff1_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT d_ff_en
PORT(
clk : IN std_logic;
reset : IN std_logic;
en : IN std_logic;
d : IN std_logic;
q : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal en : std_logic := '0';
signal d : std_logic := '0';
--Outputs
signal q : std_logic;
-- Clock period definitions
constant clk_period : time := 10ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: d_ff_en PORT MAP ( clk,reset,en,d,q);
-- Clock process definitions
process
begin
clk <= '0';
wait for 50 ns;
clk <= '1';
wait for 50 ns;
end process;
-- Stimulus process
stim_proc: process
begin
d<='1';
-- hold reset state for 100ms.
wait for 100ms;
d<='0';
wait;
end process;
END;
There is no syntax error.But there is no output also..is test bench programme is
correct.Is it necessary to correct testbench programme.Please give me the details with correction..........
