- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Is there a way to reverse a bus in systemverilog?
I am trying to do:
genvar j;
generate
for ( j=0 ; j < 256 ; j=j+1 ) begin
out[j] <= in[256-j];
end
endgenerate
But when I compile in ModelSim I get the errors:
** Error: (vlog-13069) near "[": syntax error, unexpected '['.
** Error: (vlog-13205) Syntax error found in the scope following 'out'. Is there a missing '::'?
I cannot see what is wrong here. Can anyone more familiar with SV see what is wrong?
Thanks.
- Tags:
- Cyclone® IV FPGAs
- Error
- FPGA Embedded Systems
- Intel® Quartus® Prime Software
- modelsim
- systemverilog
- Verilog
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
The problem is with the procedural assignment statement inside your generate loop. Assuming out is declared as a wire, you need to change it to
for (genvar j=0j<256;j++)
assign out[j] = in[256-j];
But there us a much simpler way of writing this without a loop using the streaming operator
assign out = {<<{in}};
Link Copied
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
The problem is with the procedural assignment statement inside your generate loop. Assuming out is declared as a wire, you need to change it to
for (genvar j=0j<256;j++)
assign out[j] = in[256-j];
But there us a much simpler way of writing this without a loop using the streaming operator
assign out = {<<{in}};

- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page