the gate level simulation hasn't any delay,why?

[HXu12]

I simulated a 32 bit adder in the gate level with Modelsim-INTEL FPGA STARTER EDITION 10.5b。The result is same as the RTL Simulution,and I cann't see any delay . Quartus edition is 17.1. Thank you!

[HXu12]

posted a file.

[HXu12]

posted a file.

[KhaiChein_Y_Intel]

Hi,

May I know what device you are using?

Thanks

[HXu12]

HI，

I am using the 5CSEMA5F31C6N device of Cyclone V family。

Thanks​

[KhaiChein_Y_Intel]

Hi,

Referring to the user guide, https://www.intel.com/content/www/us/en/programmable/documentation/gtt1529956823942.html (Simulation Levels), gate level timing simulation is not supported for Cyclone V. It is supported only for the Arria® II GX/GZ, Cyclone® IV, MAX® II, MAX® V, and Stratix® IV device families.

It is recommended to use Timing Analyzer instead of gate-level timing simulation.

Thanks.

[HXu12]

ooo，I see😃 .

thanks a lot!​