Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
17254 Discussions

timequest timing analyzer spend too much time to report timing

Altera_Forum
Honored Contributor II
1,538 Views

The timequest timing analyzer spend too much time(exceed 6hours) to report timing on one big hold violation path. I use quartusII/10.1sp1. 

Anyone have similar experience on it? Thanks a lot
0 Kudos
2 Replies
Altera_Forum
Honored Contributor II
464 Views

You mean you do something like: 

report_timing -hold -npaths 1 -from/-to -panel_name "long_report" 

and it takes 6 hours to return? Or does that include the creation of the timing netlist, reading in the .sdc, etc.? Or is it the TQ time during a full compile?  

(None of that should take 6 hours, but just trying to understand)
0 Kudos
Altera_Forum
Honored Contributor II
464 Views

On top of what Risc is asking, maybe you can give us additional information on the device family, type of design, etc. 

Can you also tell us if TimeQuest reports a warning on combinational nodes? Combinational nodes require exponential time to analyze. 

 

6hrs is not normal, so filing a case with http://mysupport.altera.com (ideally with the design) will help us debug it.
0 Kudos
Reply