timing setup failure when using altera_lvds_core20_iopll.

[johnt2]

Hello,

I am receiving several setup errors when using the altera LVDS deserializer IP in the IOPLL.

afe_rx1|u0|lvds_0|core|arch_inst|internal_pll.pll_inst|altera_lvds_core20_iopll|outclk[6]

OUTCLK[6], OUTCLK[5] and OUTCLK[2]

I saw a post discussong the IP order in assignment editor, but this did not resolve the issue.

These are all signals internal to the IP, so I don't know how to address the issue.

Thanks,

John

[TingJiangT_Intel]

Could you show the detail path in Timing analyzer and share the solution you tried.

Thanks

[TingJiangT_Intel]

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