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Altera_Forum
Honored Contributor I
841 Views

triggering options in signal tap

Hi, um kinda new to quartus ,, 

 

i wanna know what do the options in the trigger panel in signaltap means , Trigger in , Trigger out , ram size , segement size ,, etc 

 

also i want to capture the value of std logic vector in my design when its ready signal is high so how can i do this ? 

 

is there any documentation about the signaltap , may be a description or how it works ? 

 

Thanks in advance.
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Altera_Forum
Honored Contributor I
35 Views

Trigger in: an input signal from an I/O pin or internal to design used essentially as "trigger 0", the first trigger condition looked at by the tool 

Trigger out: output signal indicating that a trigger has occurred 

RAM size: number of samples of captured data you want to store in on-chip RAM; the more samples and signals monitored, the more OCRAM required 

segment size: divide up the captured data buffer into evenly sized segments, good for observing signal behavior in the design for a trigger that repeats 

 

This is all documented here in volume 3 of the Quartus Prime handbook: 

 

https://www.altera.com/products/design-software/fpga-design/quartus-prime/support.html 

 

You can get detailed training on this here: 

 

https://www.altera.com/support/training/catalog.html?coursetype=online&language=english&keywords=sig... 

 

As for your capture question, you just set up a basic AND trigger to capture data when the signal goes high. Look through the documentation and training for details.
Altera_Forum
Honored Contributor I
35 Views

 

--- Quote Start ---  

Trigger in: an input signal from an I/O pin or internal to design used essentially as "trigger 0", the first trigger condition looked at by the tool 

Trigger out: output signal indicating that a trigger has occurred 

RAM size: number of samples of captured data you want to store in on-chip RAM; the more samples and signals monitored, the more OCRAM required 

segment size: divide up the captured data buffer into evenly sized segments, good for observing signal behavior in the design for a trigger that repeats 

 

This is all documented here in volume 3 of the Quartus Prime handbook: 

 

https://www.altera.com/products/design-software/fpga-design/quartus-prime/support.html 

 

You can get detailed training on this here: 

 

https://www.altera.com/support/training/catalog.html?coursetype=online&language=english&keywords=sig... 

 

As for your capture question, you just set up a basic AND trigger to capture data when the signal goes high. Look through the documentation and training for details. 

--- Quote End ---  

 

 

Thanks alot for your help
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