try to find bitstream size and area estimates in Quartus stratix V

[Altera_Forum]

Hi 

 1. Is there a way to find bitstream size of a specific mapping in Quartus?  By using .sof file? But it seems to be for total board. Is there a way to find numbers for active/utilized part of a specific mapping?  2. How should I find the area of a mapping (not total board area, but active part of a specific mapping)?  By looking at the floorplan? But I can't find a number or scale to measure the active part.   Is there anyone who can help me out?   Thanks.

[Altera_Forum]

The bitstream always has the same size, as even the unused parts of the FPGA need to be configured. You can reduce the bitstream size in a configuration flash by using compression. 

To know how much of the FPGA is used in a project, have a look at the fitter report.

[Altera_Forum]

Thank you for your reply, Daixiwen. So do you mean utilization% (in fitter) times total size of bitstream (size of sof file) will be a good estimate of effective bitstream size?

[Altera_Forum]

"effective bitstream size" doesn't mean a lot. You always need a full bitstream to configure the FPGA, even an empty one. What exactly are you trying to find out and why?

[Altera_Forum]

I actually want to compare mapping results for the same kernel over different platforms. For FPGA part, I am using Quartus to get the latency, energy values, but area and bitstream size seems difficult to have a breakup.

[Altera_Forum]

It depends on what the value will be used for. If it is so that you know how much flash memory you need to store the configuration, then you need to use the full bitstream size. You could also use the compressed size for information, but you risk having a size that will increase even for a small change in the design.