- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
hi everyone, i have some problems in testing the following code, by knowing that i found this code in this forums, can anybody test it and tell me if he found the same problems and how to solve it.
the code is in site https://github.com/xesscorp/xula/blo...lib/hcsr04.vhd (https://github.com/xesscorp/xula/blob/master/fpga/xula_lib/hcsr04.vhd) and thnx in advance. [h=1][/h]Link Copied
9 Replies
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Instead of expecting others to do your work for you, why not tell us what problems you are having?
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
--- Quote Start --- Instead of expecting others to do your work for you, why not tell us what problems you are having? --- Quote End --- i'am not telling you to do my work i'am just asking if have a problems in compiling the program, and depend on your answer i will know what is the problem, and sorry for disturbing you sir.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
What problems are you having with it?
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Please be specific on the question, that will save your time & you can expect a quick response.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
--- Quote Start --- Please be specific on the question, that will save your time & you can expect a quick response. --- Quote End --- hi, sorry for being too late, i have this problems when compiling the previous VHDL code http://www.alteraforum.com/forum/attachment.php?attachmentid=12276&stc=1 :(:confused::confused:
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
The problem is that Quartus is made by altera for altera parts. The code you have downloaded is for a Xilinx board.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
--- Quote Start --- The problem is that Quartus is made by altera for altera parts. The code you have downloaded is for a Xilinx board. --- Quote End --- really!!!!!!! but how to know that is in xillinix, it is possible to modified it to altera vhdl?????
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Its in the Xula repository, and with 30s of searching I found it had a Xilinx chip.
What gave it away from your post was the failure to find the UNISIM library - which is a Xilinx primitives simulation library. To get it working for Altera, you'll have to strip out all references to UNISIM. If all you want is this one file - just delete the unisim library.- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
:)thnx for helping me i appreciate that, i will try to modify it and see if i get any result. :)
--- Quote Start --- Its in the Xula repository, and with 30s of searching I found it had a Xilinx chip. What gave it away from your post was the failure to find the UNISIM library - which is a Xilinx primitives simulation library. To get it working for Altera, you'll have to strip out all references to UNISIM. If all you want is this one file - just delete the unisim library. --- Quote End ---
Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page