using verilog testbench while simulating in quartus II?

[Altera_Forum]

hi all. 

 is there a way in which a verilog testbench file can be used to provide inputs for simluation in quartus II instead of using a vector waveform file?   i am aware of the way to make a verilog testbench file from a vwf file and then using the testbench file in some other eda tool. but suppose i wish to use verilog testbench in quartus and donot have a waveform file to start with...i just have the .v testbench.   thanks!  -anu

[Altera_Forum]

Use Modelsim Altera Edition. The Quartus simulator is not a testbench simulator but a waveform stiumulus simulator. (I believe you can use Tcl as a driver, which would allow you to have more "testbench-like" capabilities, but why try to describe the system behavior in the Tcl language...)

[Altera_Forum]

thanks Rysc!

[Altera_Forum]

Did I conceive a circuit under quartusII and do I want validated it by a file of data to elaborate by a program in C language, and to recover the exits as a file text, how to make?