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verilog code for SINE PWM

Altera_Forum
Honored Contributor II
2,844 Views

Hello friends.. I am trying to write verilog code for sine pwm. please check the below code and tell whether it will work or not. thank you. 

 

 

 

module sine_cos(clock, reset, en, sine, cos); 

input clock, reset, en; 

output [7:0] sine,cos; 

reg [7:0] sine_r, cos_r; 

assign sine = sine_r + {cos_r[7], cos_r[7], cos_r[7], cos_r[7:3]}; 

assign cos = cos_r - {sine[7], sine[7], sine[7], sine[7:3]}; 

always@(posedge clock or negedge reset) 

begin 

if (!reset) begin 

sine_r <= 0; 

cos_r <= 120; 

end else begin 

if (en) begin 

sine_r <= sine; 

cos_r <= cos; 

end 

end 

end 

endmodule  

 

module triangle(clock, reset, triangle); 

input clock, reset; 

output[7:0] triangle; 

reg[7:0] triangle; 

reg[7:0] counter; 

reg[7:0] updown; 

always@(posedge clock or negedge reset) 

begin 

if(reset) begin 

counter <= -125; 

updown <= 0; 

end 

else if (rising_edge(clock)) 

begin 

if (updown == 0) 

if (counter < 125) 

begin 

counter <= counter + 5; 

end 

 

if (counter == 120) 

begin 

updown <= 1; 

end 

 

else if (updown == 1) 

if (counter >-125) 

begin 

counter <= counter - 5; 

end 

 

if (counter == -120) 

begin 

updown <= 0; 

end 

end 

end 

always@(posedge clock or negedge reset) 

begin 

if(reset) begin 

triangle <= counter;  

end 

end 

endmodule  

 

 

module PWM(triangle, cos, pwm, clock); 

input triangle, cos, clock; 

output pwm; 

reg pwm; 

reg [15:0] counter = 0; 

 

always @ (posedge clock) 

 

begin 

if (cos >= triangle) pwm = 1; 

else pwm = 0; 

end 

endmodule
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Altera_Forum
Honored Contributor II
2,009 Views

did you even try and compile it yourself?

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Altera_Forum
Honored Contributor II
2,009 Views

I did run this code in quartus II, and its compilation was successful.. After that i flashed it into FPGA (cyclone II), but not getting pulses ;(;(

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Altera_Forum
Honored Contributor II
2,009 Views

where is your testbench code?

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