Re: verilog code for counter which counts in both positive and neg ede clock

Altera_Forum · ‎04-23-2014

Hi,

Anyone please help me write a counter module in verilog in which count should be incremented in both positive edge and negaive edge clock.... please help...

Thank You

Altera_Forum · ‎04-23-2014

Well, you might struggle in an FPGA, as FPGAs can only use either the rising or the falling, not both.

Altera_Forum · ‎04-23-2014

it can be do with some trick;

on slow speed you can select up or down with xored clock source

Altera_Forum · ‎04-23-2014

--- Quote Start ---

Well, you might struggle in an FPGA, as FPGAs can only use either the rising or the falling, not both.

--- Quote End ---

That's not exactly true. You can use both positive and negative edges but not to toggle the same register.

I don't do Verilog, but in VHDL it may look like this:

library IEEE;
  use IEEE.std_logic_1164.all;
  use IEEE.numeric_std.all;
entity posnegcounter is
  generic(
    WIDTH_COUNT : natural := 8
  );
  port(
    Clk     : in  std_logic;
    Reset   : in  std_logic;
    Counter : out std_logic_vector(WIDTH_COUNT - 1 downto 0)
  );
end entity posnegcounter;
architecture arch of posnegcounter is
  signal poscount : unsigned(WIDTH_COUNT - 2 downto 0); -- only need count half
  signal negcount : unsigned(WIDTH_COUNT - 2 downto 0);
begin
  process(Clk , Reset)
  begin
      if (reset = '1') then
        poscount <= to_unsigned(0, WIDTH_COUNT - 1) ;
        negcount <= to_unsigned(0, WIDTH_COUNT - 1) ;
      elsif rising_edge(Clk) then
        poscount <= poscount + 1;
      elsif falling_edge(Clk) then
        negcount <= negcount + 1;
      end if;
    end process;
  counter <= std_logic_vector(poscount + negcount);
end arch;

But still I wonder what the purpose might be?

Altera_Forum · ‎04-23-2014

Add two on every positive edge and assume odd when sampled on a negative edge (or v.v.).

Altera_Forum · ‎04-23-2014

Or generate a 2x clock...

Altera_Forum · ‎04-23-2014

At what time would you sample the counter, and using which clock? You could do something like:

reg  cnt_q;
always_ff @(posedge clk)
  cnt_q <= cnt_q + 31'd1;
   
reg lsb_q;
always_ff @(negede clk)
  lsb_q <= ~lsb_q;
wire  counter = {cnt_q, lsb_q};