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vhdl file syntax or logic error result in that ...unable open .vcd

Altera_Forum
Honored Contributor II
2,945 Views

Hi, 

 

I am new to Quartus II. I have created a very simple program for shift register in VHDL. It was successfully compiled. Then I create the input wave forms and saved it. When I run it, the last statement is "can not open .......filename .vcd file". the program runs fine, except at the end it states:  

 

reading f:/altera/worklibrary/shift/shift.vwf... 

 

reading f:/altera/worklibrary/shift/simulation/qsim/shift.msim.vcd... 

 

unable to open f:/altera/worklibrary/shift/simulation/qsim/shift.msim.vcd  

error.  

the vhdl file form the textbook"eda实用教程(vhdl版)" is: 

 

library ieee;--打开ieee库 

use ieee.std_logic_1164.all;--允许ieee库中1164程序包中所有内容 

entity shift is 

port( 

clk: in std_logic;--时钟信号 

co: in std_logic;--进位输入信号 

md: in std_logic_vector(2 downto 0); 

d: in std_logic_vector(7 downto 0);--待加载移位的数据 

qb: out std_logic_vector(7 downto 0);--led移位输出信号 

cn: out std_logic);--led移位进位信号 

end entity shift; 

architecture bhv of shift is  

signal reg:std_logic_vector(7 downto 0); 

signal cy:std_logic; 

begin 

process(clk,co,md) 

begin 

if clk'event and clk='1' then 

case md is 

when "000" =>  

reg(0)<=co;reg(7 downto 1)<=reg(6 downto 0);cy<=reg(7);--&#24102;&#36827;&#20301;&#24490;&#29615;&#21521;&#24038;&#31227;&#20301; 

when "001" =>  

reg(0)<=reg(7);reg(7 downto 1)<=reg(6 downto 0);--&#19981;&#24102;&#36827;&#20301;&#24490;&#29615;&#21521;&#24038;&#31227;&#20301; 

when "010" => 

reg(7)<=co;reg(6 downto 0)<=reg(7 downto 1);cy<=reg(0);--&#24102;&#36827;&#20301;&#24490;&#29615;&#21521;&#21491;&#31227;&#20301; 

when "011" =>  

reg(7)<=reg(0);reg(6 downto 0)<=reg(7 downto 1);--&#19981;&#24102;&#36827;&#20301;&#24490;&#29615;&#21521;&#21491;&#31227;&#20301; 

when "100" =>  

reg(7 downto 0)<=d(7 downto 0);--&#21152;&#36733;&#24453;&#31227;&#20301;&#30340;&#25968; 

when others => 

reg<=reg;cy<=cy;--&#20445;&#25345;&#19981;&#21464; 

end case;  

end if; 

end process; 

qb(7 downto 0)<=reg(7 downto 0);--led&#31227;&#20301;&#36755;&#20986; 

cn<=cy;--led&#31227;&#20301;&#36827;&#20301;&#36755;&#20986; 

end architecture bhv; 

 

 

i think that it is probably the vhdl file syntax error or logic error.signal statements are most likely to make mistakes. 

so i really need your help to solve the confused problem. 

 

thank you very much!
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8 Replies
Altera_Forum
Honored Contributor II
1,804 Views

It isn't a school project. I only find the the mistakes on the textbook. I have been pondering over it.However, I'm sorry I didn't solve it. 

 

So I am hoping to get your help. Well, come on, Is it worth it, or not?
Altera_Forum
Honored Contributor II
1,804 Views

The compiler will tell you any errors. 

It sounds like it cannot find the file  

 

The code you posted has no syntax errors. (unless it doesnt like the chinese characters)
Altera_Forum
Honored Contributor II
1,804 Views

hope qsim directory in file path indicates that you use Universtity Progrma VWF <- is it true? 

The first error i've met today face to face: after several succesive runs for functional simualtion and when I've chaged synthesis option i 've started encounter error in vt files, no any changes except for synthesis. even i try to recreate vt file. 

Try simulate in ModelSim-Altera Starter. And it is not easy provide answer when you say "Quartus II" and what simulation tool you've used. What is version number?
Altera_Forum
Honored Contributor II
1,804 Views

I deeply use the Universtity Progrma VWF button to creat the input wave forms and saved it. Even I try to recreate the VMF file. 

 

version: Quartus II 64 bit 15.0.0.145 and ModelSim-Altera 10.3d (Quartus II 15.0) 

 

Do you have any way to solve the problem. I really desire the answer. Thank you anyway.
Altera_Forum
Honored Contributor II
1,804 Views

The problem has been solved&#65281;The real reason is key word error. 

 

Error (146032): Syntax error encountered in vector source file F:/altera/WorkLibrary/shift/simulation/qsim/shift.msim.vcd, line 75, found text "reg" 

 

If you replace the word 'reg' with other word like 'temp', the waveform simulation can run normally. Thanks any way, an example in the textbook has a single mistake.
Superman
Beginner
745 Views
Altera_Forum
Honored Contributor II
1,804 Views

brr... 

really? is testbench for VHDL converted to Verilog? I heard that 'reg' is reserved word for Verilog. 

I don't trust anything from software guys until deep explorer.
Altera_Forum
Honored Contributor II
1,804 Views

Thank you! You remind me. I checked the simulation output. 

 

quartus_eda --gen_testbench --check_outputs=on --tool=modelsim_oem --format=verilog --write_settings_files=off shift -c shift --vector_source="F:/altera/WorkLibrary/shift/shift.vwf" --testbench_file="F:/altera/WorkLibrary/shift/simulation/qsim/shift.vwf.vt" 

 

Fact like you said truly.
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