vhdl real time clock

[Altera_Forum]

Can you please help me with this task..I am having huge problems 

    Design and implement a circuit on your DE-series board that acts as a real-time clock. It should display the minutes (from 0 to 59) on HEX5 − 4, the seconds (from 0 to 59) on HEX3 − 2, and hundredths of a second (from 0 to 99) on HEX1 − 0. Use the switches SW7−0 to preset the minute part of the time displayed by the clock when KEY1 is pressed. Stop the clock whenever KEY0 is being pressed and continue the clock when KEY0 is released

[Altera_Forum]

What problems are you having so far? 

Have you written any code? Have you written a testbench?

[Altera_Forum]

library ieee; 

use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;  entity real_time_clock is port (clk1 : in std_logic;  seconds : out std_logic_vector(5 downto 0);  minutes : out std_logic_vector(5 downto 0);  miliseconds: out std_logic_vector(4 downto 0);  hex0,hex1,hex2,hex3,hex5,hex5 (o to 6)  ); end real_time_clock ;  architecture Behavioral of real_time_clock is signal sec,min,mili : integer range 0 to 60 :=0; signal count : integer :=1; signal clk : std_logic :='0'; begin seconds <= conv_std_logic_vector(sec,6); minutes <= conv_std_logic_vector(min,6); miliseconds<= conv_std_logic_vector(mili,5);   --clk generation.For 100 MHz clock this generates 1 Hz clock. process(clk1) begin if(clk1'event and clk1='1') then count <=count+1; if(count = 50000000) then clk <= not clk; count <=1; end if; end if; end process;  process(clk) --period of clk is 1 second. begin  if(clk'event and clk='1') then sec <= sec+ 1; if(sec = 59) then sec<=0; min <= min + 1; if(min = 59) then hour <= hour + 1; min <= 0; if(hour = 23) then hour <= 0; end if; end if; end if; end if;  end process;  end Behavioral;     -------------------------------------bcd seven segment-----------------------------------------------------------    LIBRARY ieee;  USE ieee.std_logic_1164.all;  ENTITY bcd7seg IS  PORT ( bcd : IN STD_LOGIC_VECTOR(3 DOWNTO 0);  display : OUT STD_LOGIC_VECTOR(0 TO 6));  END bcd7seg;  ARCHITECTURE Behavior OF bcd7seg IS  BEGIN  PROCESS (bcd)  BEGIN  CASE bcd IS  WHEN "0000" => display <= "0000001";  WHEN "0001" => display <= "1001111";  WHEN "0010" => display <= "0010010";  WHEN "0011" => display <= "0000110";  WHEN "0100" => display <= "1001100";  WHEN "0101" => display <= "0100100";  WHEN "0110" => display <= "0100000";  WHEN "0111" => display <= "0001111";  WHEN "1000" => display <= "0000000";  WHEN "1001" => display <= "0000100";  WHEN OTHERS => display <= "1111111";  END CASE;  END PROCESS;  END Behavior;        THIS IS THE CODE..A LITTLE BIT NOT CLEAR, AND HAS STILL TO WORK ON IT. BUT BIGGEST PROBLEM IS THAT I DON'T KNOW HOW TO CONNECT OUTUPUTS TO SEVEN SEGMENT DISPLAY. I DON'T KNOW HOW TO CONNECT FOR EXAMPLE SECONDS TO HEX4,5....AND HOW TO CHANGE MINUTES USING SW7 DONWTO O

[Altera_Forum]

Your problems are not very clear? have you got a quartus project? have you assigned the pinout from the top level to the seven seg display?