vhdl signal delay block code randomly not working

[mcorr16]

Hello,

I'm trying to run a signal delay block I coded in VHDL on an Altera MAX II. It works "normally" but sometimes it seems it doesn't apply the delay as expexted. Do you have any idea of what I did wrong?

Thanks

Michele

LIBRARY IEEE;

USE IEEE.std_logic_1164.ALL;

use IEEE.std_logic_arith.all;

use IEEE.std_logic_unsigned.all;

use IEEE.Numeric_std.all;

ENTITY Delay IS

PORT

(

input    : IN std_logic;

delayType : IN std_logic;

clk : IN std_logic;

output : OUT std_logic

);

END Delay;

ARCHITECTURE Delay_signals OF Delay IS

  signal output_status : std_logic;

signal status_counter : std_logic_vector(7 downto 0);

signal counter_thr: std_logic_vector(7 downto 0);

BEGIN

PROCESS (clk, input, delayType, output_status)

BEGIN

IF delayType = '0' THEN

-- GateDelay for external 2 us = 80 ticks

counter_thr <= B"01010000";

ELSE

-- Internal IGBTs delay 3.5 us = 140 ticks

counter_thr <= B"10001100";

END IF;

IF rising_edge(clk) THEN

IF input = '1' THEN

IF output_status = '0' THEN

status_counter <= status_counter + 1;

-- 1 us = 40 ticks

IF status_counter > counter_thr THEN

output_status <= '1';

status_counter <= (others => '0');

END IF;

ELSE

status_counter <= (others => '0');

END IF;

ELSE

IF output_status = '1' THEN

status_counter <= status_counter + 1;

IF status_counter > counter_thr THEN

output_status <= '0';

status_counter <= (others => '0');

END IF;

ELSE

status_counter <= (others => '0');

END IF;

END IF;

END IF;

output <= output_status;

END PROCESS;

END Delay_signals;

[Vicky1]

Hi,

Have you verified the functionality of your design by writing the testbench?

Please share here simulation screenshot & elaborate your observation.

Regards,

Vicky

[mcorr16]

​Hi,

I didn't write the testbench. I'm using the MAX II to route some signals using a main schematic file, .bdf, where I do some AND&OR logics: it's a 10 years old design. I recently tried to add some delays with the code I posted and I noticed that normally the input signal is correctly delayed with the forecasted value: it just randomly cuts the delay at the rise or fall. It seems like my "static variable" output_status sometimes doesn't retain the correct value more than a clock issue because otherwise I would expect to experience some random effects also on the value of the delay applied instead or the delay is right there (most of the times) or it's cut.

Maybe it's worth to say that I'm using this block multiple times in the schematic

thanks for your support.

Regards

Michele

[Vicky1]

Hi Michele,

"Hi,

Have you verified the functionality of your design by writing the testbench?

Please share here simulation screenshot & elaborate your observation.

Regards,

Vicky" --------- I would like to suggest before implementing any design(HDL or schematic) on board you should verify the functionality of the design writing testbench & tracing the simulation waveforms so if you want to clarify your issue, please provide screenshot of your simulation window.

Regards,

Vicky

[Vicky1]

Hi,

May I know any update or Should I consider that case to be closed?

Regards,

Vicky

[mcorr16]

​Hello,

 yes I solved the issue. It was not linked to my VHDL design but to metastability problem

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/wp/wp-01082-quartus-ii-metastability.pdf

Passing all my inputs through a flip-flop solved I the problem.

thanks

regards

Michele