I migrated an Arria 10 SoC project from 18.1 to 19.3. HPS DDR4 is in banks 2K and 2J. The RZQ is in Bank 2I. This was allowed before as Early IO Release is not being used. Is there an INI for the old behavior?

[BHoey]

I know that the preference is for the RZQ to be with the rest of the signals and on newer PCBs we've moved it but I still need to build for this board.

Which release changed this rule?

[Fawaz_Al-Jubori]

Hello,

Kindly check the workaround in this link below:

https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/emif/2018/are-there-any-placement-restrictions-for-the-intel-stratix-10-hp.html

Please let me know if this could help to fix the issue.

Thank you

[BHoey]

That link is for Stratix 10 where this is for Arria 10. Assuming the workaround is the same, this kdb entry does not publish the workaround but states to contact Intel. Intel support directs me here to the Forum. Can you supply the workaround?

Thanks

-Brian