vital glitch in my clock pattern.

[Altera_Forum]

hi team, 

i generated a clock pattern using Libero software.but after post layout simulation .vital glitches are coming.i dont know how to remove it?? this is the code i written and testbench.please help me.  hi sir, please help me sir. i need ur help. me a trainee in a small electronics company named synergy in kerala.they gave a task to generate a waveform.i wrote vhdl program . after post layout simulation,i got vital glitch. i dont know how to remove this in actel libero. please help me.    top .docx : main program aaaaaa.docx: testbench   untiled jpg : image after first simulation means..what is the expected output glitch jpg: final image output but not coorct because of glitch problem.     after checking my program can u give your valuable suggestions to avoid vital glitch?????????    

[Altera_Forum]

Post the images in a pdf file as well. They are too small here.

[Altera_Forum]

Its probably because your counter changes on the falling edge, and the state machine changes on the rising edge of the clock. Any reason why you did this? did you provide an SDC file that accounted for this half-clock cycle timing relationship?

[Altera_Forum]

helo sir i included the image in pdf format. sir,please 

go through my program and please tell me where is the orgin of vital glitch...i am doing simulation in modelsim actel libero.