vlog-7 "Failed to open design unit file in read mode" error during simulation for Agilex7 board

[NoahHuguenin]

Good day, 

I am trying to simulate an HLS for an Agilex7 device.

I'm using Quartus Prime Pro 24.2, and the corresponding versions of Questa - Intel FPGA Edition and HLS Compiler. Running on a Windows 11 Pro 23H2 computer.

After launching compilation, simulation, etc. on the command window, the following message results: 

HLS Elaborate verification testbench FAILED.
See (...)/luinv.prj/debug.log for details.
Error: Cosim testbench elaboration failed.

When opening said debug.log, this is the only error present: 

# Top level modules:
# dpic_invmatrixursi
# End time: 12:55:10 on Jan 23,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 12:55:10 on Jan 23,2025
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 -suppress 7061 ../../ip/tb/cat_cwfsw/avalon_concatenate_singlebit_conduits_10/sim/cat_cwfsw_avalon_concatenate_singlebit_conduits_10_lrbideq.sv -work avalon_concatenate_singlebit_conduits_10
# ** Error: (vlog-7) Failed to open design unit file "../../ip/tb/cat_cwfsw/avalon_concatenate_singlebit_conduits_10/sim/cat_cwfsw_avalon_concatenate_singlebit_conduits_10_lrbideq.sv" in read mode.
# No such file or directory. (errno = ENOENT)
# End time: 12:55:10 on Jan 23,2025, Elapsed time: 0:00:00
# Errors: 1, Warnings: 0
# ** Error: c:/intelFPGA_pro/24.2/questa_fe/win64/vlog failed.
# Executing ONERROR command at macro ./msim_compile.tcl line 7
# Errors: 1, Warnings: 0

I checked whether the file exists, and apparently it does. It is in the specified folder, and has full permissions as far as I can tell. 

The error appears when running msim_compile.tcl, which is located at (...)/luinv.prj/verification/tb/sim/

The file-path which causes the error is then: 

(...)/luinv.prj/verification/ip/tb/cat_cwfsw/avalon_concatenate_singlebit_conduits_10/sim/cat_cwfsw_avalon_concatenate_singlebit_conduits_10_lrbideq.sv

Here is the path in which the file is present in my computer, followed by the path from the log:

(...)/luinv.prj/verification/ip/tb/cat_cwfsw/avalon_concatenate_singlebit_conduits_10/sim/cat_cwfsw_avalon_concatenate_singlebit_conduits_10_lrbideq.sv

(...)/luinv.prj/verification/ip/tb/cat_cwfsw/avalon_concatenate_singlebit_conduits_10/sim/cat_cwfsw_avalon_concatenate_singlebit_conduits_10_lrbideq.sv

I include it here in case I may be unwittingly blind, but I see no difference between these paths. 

Any ideas on what may cause this error?

Thank you and regards, 

Noah 

[BoonBengT_Altera]

Hi @NoahHuguenin,

Thank you for posting in Intel community forum, hope all is well and apologies for the delayed in response due to the holiday season.

Noted on the error message, could you provide us which HLS example design specifically that you are trying to simulate?

Just to insolate the problem further, you are able to simulate other none HLS design with Questa before?

Error seems to be complaining no such files, hence it could be some incorrect path specified as you have validate the files already exist.

Best Wishes

BB

[BoonBengT_Altera]

Hi @NoahHuguenin,

Good day, just following up on the previous clarification.

By any chances did you managed to look into it?

Hope to hear from you soon.

Best Wishes

BB

[NoahHuguenin]

Hello @BoonBengT_Altera! 

Please excuse my delay.

I have been able to simulate other HLS projects for the same target device, so perhaps the issue lies with this specific component. 

I cannot share the project for reasons of confidentiality, but it deals with matrix inversion. 

I was thinking about whether it would be possible to create a different example project that also uses this component which results in error, but I am not sure how to do that! 

About the incorrect path, it seems like it appears correctly on the log.

I checked the absolute path length in case it was too long. The total character count from the disk to the file, both included, is 248 characters. That is close to the maximum path length, but not quite, if I am not mistaken.

I will let you know if I find something like that. Meanwhile, I share this clarification that I have been able to successfully simulate other projects.

Regards,

Noah

[BoonBengT_Altera]

Hi @NoahHuguenin,

Noted on the success simulation for other project and environment path, that rules out the possibilities for platform/tools setup issues. Hence it would be more toward the code related cause.

Agree on the suggestion on creating a different example project to identify the error component. I would suggest the following:

- creating a different example for the previous success simulate project by adding the component from the matrix inversion project OR

- removing each component one by one in the matrix inversion project, followed by building/compiling the project to identify the project.

Hope that clarify.

Best Wishes

BB

[NoahHuguenin]

Hello @BoonBengT_Altera 

Thank you for the recommendations, I will work on that to hopefully provide a design which I can share to see if the error can be replicated.

Meanwhile, while trying to simulate a parallel project, I received a similar error: 

# ** Error: (vlog-7) Failed to open design unit file "../../../components/channel_compensation/channel_compensation/channel_compensation_internal_10/sim/channel_compensation_i_iowr_bl_eststream0000hannel_compensation0.sv" in read mode.
# No such file or directory. (errno = ENOENT)

This time it is apparent that the unit involved has something to do with a Stream Interface (estStream) for my channel_compensation component, but again, this file does seem to exist in the specified folder.

Perhaps this indicates that the previous error was not an isolated problem.

In any case, I hope to be back soon with a design to share.

Thank you and regards, 

Noah

[NoahHuguenin]

Hello once more @BoonBengT_Altera! 

I don't have a design to share, but I have interesting news nonetheless. 

I have tried making multiple changes to the design (and, in particular, to the confidential part of it), and all the changes I have tried seemed to resolve the error, so I cannot share a design replicating it. 

For example, changing the name of the component from "channel_compensation" to "c_comp" solves the error. 

I tried some other smaller changes, but most surprisingly, reverting to the original code after that did not throw the error. 

This was for the second design that I mentioned. The original design which threw a similar error also worked after shortening both the component name and changing the directory to one with a shorter path.

My guess is that it did in fact have something to do with maximum path length. This does not really explain why one of the designs failed, then worked again after changing it and undoing the changes...

But in any case, I no longer have a problem when trying to simulate my designs. 

My advice for anyone facing a similar problem: try shortening the path and the component name. 

Thank you and excuse me for not being able to provide clearer information! 

Regards,

Noah

[BoonBengT_Altera]

Hi @NoahHuguenin,

Greetings, Good to know that you managed to overcome this and thank you for sharing the troubleshooting steps for the benefit for others. With no further clarification on this thread, it will be transitioned to community support for further help on doubts in this thread. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Thank you for the questions and as always pleasure having you here.

Best Wishes

BB