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Hi All,
I am completely new to this forum and to the Quartus II software and am seeking a bit of guidance. I make a program of prime number detector in the vhdl file. here is the code
library ieee;
use ieee.std_logic_1164.all;
entity primedetector is
port (I2,I1,I0: in std_logic;
F: out std_logic);
end primedetector;
architecture persamaan_logika of primedetector is
begin
F<= (not I2 and I0) or (I2 and I1);
end persamaan_logika;
but when i run to create simulation waveform editor and run the simulation. the result is not as i expected. it shows the wrong value. here is the pict of it https://www.alteraforum.com/forum/attachment.php?attachmentid=14463&stc=1 and also i can't run the modelsim simulation. anyone has any idea what i suppose to do? i'm using quartus II 64 bit version 13.0
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Whats wrong with the sim? it looks correct to me.
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--- Quote Start --- Whats wrong with the sim? it looks correct to me. --- Quote End --- then why is this always happen when i simulate with multisim? https://www.alteraforum.com/forum/attachment.php?attachmentid=14466 https://www.alteraforum.com/forum/attachment.php?attachmentid=14467 here goes what it says
Device family: Cyclone II
Running quartus eda_testbench
>> quartus_eda --gen_testbench --check_outputs=on --tool=modelsim_oem --format=verilog dekprim -c dekprim {--vector_source=D:/altera/13.0sp1/dekprim2/dekprim.vwf} {--testbench_file=./simulation/qsim/dekprim.vt}
PID = 14444
Can't contact license server "27000@falithurrahman" -- this server will be ignored
*******************************************************************
Running Quartus II 64-Bit EDA Netlist Writer
Version 13.0.0 Build 156 04/24/2013 SJ Web Edition
Processing started: Sat Nov 25 22:12:26 2017
Command: quartus_eda --gen_testbench --check_outputs=on --tool=modelsim_oem --format=verilog dekprim -c dekprim --vector_source=D:/altera/13.0sp1/dekprim2/dekprim.vwf --testbench_file=./simulation/qsim/dekprim.vt
Generated Verilog Test Bench File ./simulation/qsim/dekprim.vt for simulation
Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 1 warning
Peak virtual memory: 463 megabytes
Processing ended: Sat Nov 25 22:12:28 2017
Elapsed time: 00:00:02
Total CPU time (on all processors): 00:00:01
Running quartus eda_func_netlist
>> quartus_eda --functional=on --simulation --tool=modelsim_oem --format=verilog dekprim -c dekprim
PID = 13876
Can't contact license server "27000@falithurrahman" -- this server will be ignored
*******************************************************************
Running Quartus II 64-Bit EDA Netlist Writer
Version 13.0.0 Build 156 04/24/2013 SJ Web Edition
Processing started: Sat Nov 25 22:12:28 2017
Command: quartus_eda --functional=on --simulation=on --tool=modelsim_oem --format=verilog dekprim -c dekprim
Generated file dekprim.vo in folder "D:/altera/13.0sp1/dekprim2/simulation/modelsim/" for EDA simulation tool
Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 1 warning
Peak virtual memory: 463 megabytes
Processing ended: Sat Nov 25 22:12:31 2017
Elapsed time: 00:00:03
Total CPU time (on all processors): 00:00:01
*******************************************************************
Running quartus modelsim
>> vsim -c -do dekprim.do
PID = 6328
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--- Quote Start --- Whats wrong with the sim? it looks correct to me. --- Quote End --- it shows high logic when the binary is 001(1) but doesn't even turn high when the binary is 010 (2). and why cant i run simulation with modelsim? this thing always shows error occured during modelsim simulation https://alteraforum.com/forum/attachment.php?attachmentid=14468&stc=1 https://alteraforum.com/forum/attachment.php?attachmentid=14469&stc=1
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--- Quote Start --- it shows high logic when the binary is 001(1) but doesn't even turn high when the binary is 010 (2). --- Quote End --- Because your logic means that 010 forces F low. And I dont see an error in the modelsim window..
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--- Quote Start --- Because your logic means that 010 forces F low. And I dont see an error in the modelsim window.. --- Quote End --- https://alteraforum.com/forum/attachment.php?attachmentid=14471&stc=1 https://alteraforum.com/forum/attachment.php?attachmentid=14471&stc=1 the words in red circle shows error occured during multisim simulation, and after that nothing happened.
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Check the log, or further back in the transcript, what the error actually was. What you have posted does not show any errors. Just a warning about ignoring a licence server.
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If you've installed Modelsim Altera/Intel edition, then to enable the tool, you need to specify the installation path in the Quartus tool. To do so, do the following.
1. Launch Quartus tool 2. From the menu choose Tools --> Options. 3. In this Options window, look at the list in the left pane. Select "EDA Tool Options" from the list. 4. Now, in the right pane, you will see a list of tools with blank text boxes. Choose the box with [...] next to ModelSim. 5. Browse to the location of Modelsim installation and point to the Win32 folder.. for example .. C:\intelFPGA\17.1\modelsim_ase\win32aloem . 6. Click the "Select Folder' button and close the windows. Now, you can launch ModelSim from the Quartus menu for Simulations. Provided you have a valid license for it.- Mark as New
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Apart from all confusion about unclear or non-existing error messages, I understand that you are referring to the different waveforms for signal F in post# 1 versus# 3 etc.
Unfortunately you don't show the design or test bench generating the waveform. I can just guess that it's a typical simulation to synthesis inconsistency problem, e.g. due to an incomplete sensitivity list. They are ignored in synthesis and respectively gate level simulation but required in functional simulation. Please provide the complete code and we may understand the problem.
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