waveform simulation producing no output (xx) in Quartus II

[TGuo0]

Hello. So I am trying to simulate a simple JK flip-flop, and for some reason, when I try to do so, Q and Qbar stay as XX. The simulation works if I remove the clock. I don't know why that would affect anything. Please help me. I'm just a poor college student trying to graduate.

[Vicky1]

Hi Tina, Please help me by providing below details, 1. which quartus(edition & version) are you using? 2. have you come across any error while simulating including clock signal? 3. provide the simulation screenshot of the result without clock signal Thanks, Vikas

[TGuo0]

Hello!

1. I'm using Quartus II Web Edition 13.0sp1
2. The screenshot above is what happens when I include clock signal
3. The below is what happens when the clock signal to both latches are the same (so the not gate at the bottom is removed)

[Abe]

The simulation does not work due to the inherent behavior of the JK master slave FF:

1. If CLK is low at the start, the outputs Q and Qb will be X irrespective of the state of J and K.
2. If CLk is high at the start and J=0 and K=1, the outputs will still be X. (K input is also Reset for SR flop which is used to build the JK master-slave)

To get the simulation working,

1. Shift the clock edge by some x ns so that it starts HIGH.
2. Assign J =1 and K = 0 , this is the set condition for the FF.
3. Follow the rest of the JK FF truth table.

[TGuo0]

Thanks for the clarification! Unfortunately, when I tried your suggestions, the same result came out. Is there something I'm missing?

 

[Abe]

Take a look at the following projet file. It should help you. It also includes the waveform for simulation.

[TGuo0]

Thanks so much!