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17268 Discussions

where is my fault in this code?

Altera_Forum
Honored Contributor II
2,116 Views

when I attempt to simulate the design This warning is displayed: 

warning: daggen_0523: the source is compiled without the -dbg switch. line breakpoints, code coverage, and assertion debug will not be available. 

where is my fault? 

library IEEE;use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity RAM_1 is generic ( M : natural:=8 ); -- depth=2**N port( clk : in std_logic; -- clock cs : in std_logic; -- chip select rw : in std_logic; -- read=0/write=1 addr : in integer; -- address data : inout std_logic_vector(7 downto 0)); -- data end entity RAM_1; architecture RTL of RAM_1 is type mem_array is array (0 to M**2-1) of std_logic_vector(7 downto 0); signal ram : mem_array:=( X"06",X"02",X"0A",X"06",X"05",X"03",X"07",X"09", X"02",X"01",X"00",X"06",X"08",X"0B",X"04",X"0F", X"06",X"02",X"0A",X"06",X"05",X"03",X"07",X"09", X"02",X"01",X"00",X"06",X"08",X"0B",X"04",X"0F", X"06",X"02",X"0A",X"06",X"05",X"03",X"07",X"09", X"02",X"01",X"00",X"06",X"08",X"0B",X"04",X"0F", X"06",X"02",X"0A",X"06",X"05",X"03",X"07",X"09", X"02",X"01",X"00",X"06",X"08",X"0B",X"04",X"0F" ); begin process begin wait until ( CLK'event and CLK='1'); if cs='1' then if rw='1' then ram(addr) <= data; else data <= ram(addr); end if; else data <= (others=>'Z'); end if; end process; end RTL;
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Altera_Forum
Honored Contributor II
1,192 Views

As far as I understand it is a warning becouse you have disabled an option in your simulation software. It tells you that you have disabled debug options. I have no experience with this, but I suggest you take a look at the options. 

 

[edit] 

I put the error message in a websearch and this was the first result. Does this help? 

http://www.aldec.com/en/support/resources/documentation/faq/1005
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Altera_Forum
Honored Contributor II
1,192 Views

thanks alot my friend,i saw it before 

u r right 

this code work singleness 

but when i use it in a program it doesn't work.i thought maybe the problem is because of this warning.
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Altera_Forum
Honored Contributor II
1,192 Views

I am unfamiliar with the program used for simulation. Do you use a testbench file? It may be that there is a problem with the stimuli.

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Altera_Forum
Honored Contributor II
1,192 Views

please clarify - "it doesnt work" with a more detailed description of what doesnt work any why.

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