wire assignment in verilog

[junyoung2]

Hello, I have a question while I was writing the code. I made a code wire [15:0] A; and I declared input B; and I declared this signal as assign A = {8{B}};. When I declared this, the top 8 bits of signal A would be filled with 0, so why would it be filled with 0? Shouldn't it be filled with z or x??

[sstrell]

No.  Z (high impedance) or X (don't care) are not valid logic levels internal to the hardware of the FPGA.  So anything not defined has to go to 0.  They could be X in a simulation depending on your design if that's what you mean.

Quartus provides warning messages when vector sizes don't match like this.