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Agilex 5 EMAC to EMAC : Driver error

K606
New Contributor III
‎06-17-2025 04:11 AM
8,212 Views
Solved Jump to solution

I am trying to ping one EMAC from another, and have instantiated the following in the HPS:

K606_1-1750158095929.png

These are exported to the top level, then connected as followed:

// https://www.intel.com/content/www/us/en/docs/programmable/814346/25-1/fpga-emac-i-o-signals.html
module dual_emac_interface (
    input  wire        clk,
    input  wire        rst_n,

    // EMAC0 Signals
    input  wire        emac0_app_rst_reset_n_wire,
    output wire        emac0_mac_tx_clk_o_wire,     // not used in 10/100 Mbps
    input  wire        emac0_mac_tx_clk_i_wire,     // not used in 1/2.5 Gbps 
    input  wire        emac0_mac_rx_clk_wire,
    output wire        emac0_mac_rst_tx_n_wire,     // (unused) reset for tx path
    output wire        emac0_mac_rst_rx_n_wire,     // (unused) reset for rx path
    output wire        emac0_mac_txen_wire,
    output wire        emac0_mac_txer_wire,
    input  wire        emac0_mac_rxdv_wire,
    input  wire        emac0_mac_rxer_wire,
    input  wire [7:0]  emac0_mac_rxd_wire,          // for 10/100 Mbps designs, only bits [3:0] are used
    input  wire        emac0_mac_col_wire,          // valid only when operating in half duplex
    input  wire        emac0_mac_crs_wire,
    output wire [2:0]  emac0_mac_speed_wire,        // set to 3'b011 for 1 Gbps (125 MHz)
    output wire [7:0]  emac0_mac_txd_o_wire,        // for 10/100 Mbps designs, only bits [3:0] are used

    // EMAC1 Signals
    input  wire        emac1_app_rst_reset_n_wire,
    output wire        emac1_mac_tx_clk_o_wire,
    input  wire        emac1_mac_tx_clk_i_wire,
    input  wire        emac1_mac_rx_clk_wire,
    output wire        emac1_mac_rst_tx_n_wire,
    output wire        emac1_mac_rst_rx_n_wire,
    output wire        emac1_mac_txen_wire,
    output wire        emac1_mac_txer_wire,
    input  wire        emac1_mac_rxdv_wire,
    input  wire        emac1_mac_rxer_wire,
    input  wire [7:0]  emac1_mac_rxd_wire,
    input  wire        emac1_mac_col_wire,
    input  wire        emac1_mac_crs_wire,
    input  wire [2:0]  emac1_mac_speed_wire,
    output wire [7:0]  emac1_mac_txd_o_wire
);
    assign emac0_app_rst_reset_n_wire = rst_n;
    //assign emac0_mac_tx_clk_i_wire = clk;                
    assign emac0_mac_rx_clk_wire = emac1_mac_tx_clk_o_wire; //rxclk0=txclk1
    assign emac0_mac_rxdv_wire = 1'b1;                      //valid held high
    assign emac0_mac_rxer_wire = emac1_mac_txer_wire;       //rx0err=tx1err
    assign emac0_mac_rxd_wire = emac1_mac_txd_o_wire;       //din0=dout1
    //assign emac0_mac_col_wire = 1'b0;                     //full duplex
    assign emac0_mac_crs_wire = 1'b1;                       //never idle

    assign emac1_app_rst_reset_n_wire = rst_n;
    //assign emac1_mac_tx_clk_i_wire = clk;                     
    assign emac1_mac_rx_clk_wire = emac0_mac_tx_clk_o_wire;    
    assign emac1_mac_rxdv_wire = 1'b1;                         
    assign emac1_mac_rxer_wire = emac0_mac_txer_wire;           
    assign emac1_mac_rxd_wire = emac0_mac_txd_o_wire;           
    //assign emac1_mac_col_wire = 1'b0;                         
    assign emac1_mac_crs_wire = 1'b1;                                

endmodule

In the .dts, I have the following config (based on the dtsi provided by altera

&gmac0 {
	status = "okay";
	phy-mode = "gmii";

	fixed-link {
		speed = <1000>;
		full-duplex;
	};
};

&gmac1 {
	status = "okay";
	phy-mode = "gmii";

	fixed-link {
		speed = <1000>;
		full-duplex;
	};
};

 However, when booting into linux - the drivers appear to be unhappy:

[   26.367856] socfpga-dwmac 10810000.ethernet: Failed to reset the dma
[   26.374250] socfpga-dwmac 10810000.ethernet eth0: stmmac_hw_setup: DMA engine initialization failed
[   26.383425] socfpga-dwmac 10810000.ethernet eth0: __stmmac_open: Hw setup failed
[   26.588347] socfpga-dwmac 10820000.ethernet: Failed to reset the dma
[   26.594740] socfpga-dwmac 10820000.ethernet eth1: stmmac_hw_setup: DMA engine initialization failed
[   26.603759] socfpga-dwmac 10820000.ethernet eth1: __stmmac_open: Hw setup failed

 

Anyone maybe know what is the issue?

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K606
New Contributor III
‎06-24-2025 07:36 AM
6,946 Views
Solved Jump to solution

Solved: bring MAC signals up a module

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18 Replies
Sparrow_Altera
Employee
‎06-17-2025 09:27 AM
8,160 Views
Solved Jump to solution

Hello

Can you send your .dtsi file.

Sharing links to EMAC sections in our doc to check

HPS EMAC Design Guidelines and Examples

HPS EMAC Design Considerations - EMAC GMII through FPGA Fabric

 

We also have couple of example designs below, you can check

Example Designs

Agilex 5 TSN HPS RGMII System Example Design - TSN HPS RGMII System Example Design

Agilex 5 TSN HPS RGMII System Example Design - TSN RGMII HVIO System Example Design

Agilex 5 TSN SGMII XCVR System Example Design - TSN SGMII XCVR System Example Design

 

Thanks

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K606
New Contributor III
‎06-17-2025 09:33 AM
8,154 Views
Solved Jump to solution

Hi thanks for the resources!

yes no problem, here is the .dtsi:

// SPDX-License-Identifier:     GPL-2.0
/*
 * Copyright (C) 2023, Intel Corporation
 */

/dts-v1/;
#include <dt-bindings/reset/altr,rst-mgr-agilex5.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/agilex5-clock.h>

/ {
	compatible = "intel,socfpga-agilex";
	#address-cells = <2>;
	#size-cells = <2>;

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		service_reserved: svcbuffer@0 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x80000000 0x0 0x2000000>;
			alignment = <0x1000>;
			no-map;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a55";
			device_type = "cpu";
			enable-method = "psci";
			reg = <0x0>;
			next-level-cache = <&L2>;
		};

		cpu1: cpu@1 {
			compatible = "arm,cortex-a55";
			device_type = "cpu";
			enable-method = "psci";
			reg = <0x100>;
			next-level-cache = <&L2>;
		};

		cpu2: cpu@2 {
			compatible = "arm,cortex-a76";
			device_type = "cpu";
			enable-method = "psci";
			reg = <0x200>;
			next-level-cache = <&L2>;
		};

		cpu3: cpu@3 {
			compatible = "arm,cortex-a76";
			device_type = "cpu";
			enable-method = "psci";
			reg = <0x300>;
			next-level-cache = <&L2>;
		};

		L2: l2-cache {
			compatible = "cache";
			cache-level = <2>;
			next-level-cache = <&L3>;
		};

		L3: l3-cache {
			compatible = "cache";
		};

	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	intc: interrupt-controller@1d000000 {
		compatible = "arm,gic-v3", "arm,cortex-a15-gic";
		#interrupt-cells = <3>;
		#address-cells = <2>;
		#size-cells =<2>;
		interrupt-controller;
		#redistributor-regions = <1>;
		label = "GIC";
		status = "okay";
		ranges;
		redistributor-stride = <0x0 0x20000>;
		reg = <0x0 0x1d000000 0 0x10000>,
			<0x0 0x1d060000 0 0x100000>;

		its: msi-controller@1d040000 {
			compatible = "arm,gic-v3-its";
			reg = <0x0 0x1d040000 0x0 0x20000>;
			label = "ITS";
			msi-controller;
			status = "okay";
		};
	};

	/* Clock tree 5 main sources*/
	clocks {
		cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
		};

		cb_intosc_ls_clk: cb-intosc-ls-clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
		};

		f2s_free_clk: f2s-free-clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
		};

		osc1: osc1 {
			#clock-cells = <0>;
			compatible = "fixed-clock";
		};

		qspi_clk: qspi-clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <200000000>;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupt-parent = <&intc>;
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
	};

	usbphy0: usbphy {
		#phy-cells = <0>;
		compatible = "usb-nop-xceiv";
	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupt-parent = <&intc>;
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
		cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		device_type = "soc";
		interrupt-parent = <&intc>;
		ranges = <0 0 0 0xffffffff>;

		base_fpga_region {
			#address-cells = <0x2>;
			#size-cells = <0x2>;
			compatible = "fpga-region";
			fpga-mgr = <&fpga_mgr>;
		};

		clkmgr: clock-controller@10d10000 {
			compatible = "intel,agilex5-clkmgr";
			reg = <0x10d10000 0x1000>;
			#clock-cells = <1>;
		};

		gmac0: ethernet@10810000 {
			compatible = "altr,socfpga-stmmac-a10-s10",
				     "snps,dwxgmac-2.10",
				     "snps,dwxgmac";
			reg = <0x10810000 0x3500>;
			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "macirq",
					  "macirq_tx0",
					  "macirq_tx1",
					  "macirq_tx2",
					  "macirq_tx3",
					  "macirq_tx4",
					  "macirq_tx5",
					  "macirq_tx6",
					  "macirq_tx7",
					  "macirq_rx0",
					  "macirq_rx1",
					  "macirq_rx2",
					  "macirq_rx3",
					  "macirq_rx4",
					  "macirq_rx5",
					  "macirq_rx6",
					  "macirq_rx7";
			resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
			reset-names = "stmmaceth", "stmmaceth-ocp";
			clocks = <&clkmgr AGILEX5_EMAC0_CLK>,
				 <&clkmgr AGILEX5_EMAC_PTP_CLK>;
			clock-names = "stmmaceth", "ptp_ref";
			mac-address = [00 00 00 00 00 00];
			tx-fifo-depth = <32768>;
			rx-fifo-depth = <16384>;
			snps,multicast-filter-bins = <64>;
			snps,perfect-filter-entries = <64>;
			snps,axi-config = <&stmmac_axi_emac0_setup>;
			snps,mtl-rx-config = <&mtl_rx_emac0_setup>;
			snps,mtl-tx-config = <&mtl_tx_emac0_setup>;
			snps,pbl = <32>;
			snps,pblx8;
			snps,multi-irq-en;
			snps,tso;
			snps,rx-vlan-offload;
			altr,sysmgr-syscon = <&sysmgr 0x44 0>;
			altr,smtg-hub;
			iommus = <&smmu 1>;

			status = "disabled";

			stmmac_axi_emac0_setup: stmmac-axi-config {
				snps,wr_osr_lmt = <31>;
				snps,rd_osr_lmt = <31>;
				snps,blen = <0 0 0 32 16 8 4>;
			};

			mtl_rx_emac0_setup: rx-queues-config {
				snps,rx-queues-to-use = <8>;
				snps,rx-sched-sp;
				queue0 {
					snps,dcb-algorithm;
					snps,map-to-dma-channel = <0x0>;
				};
				queue1 {
					snps,dcb-algorithm;
					snps,map-to-dma-channel = <0x1>;
				};
				queue2 {
					snps,dcb-algorithm;
					snps,map-to-dma-channel = <0x2>;
				};
				queue3 {
					snps,dcb-algorithm;
					snps,map-to-dma-channel = <0x3>;
				};
				queue4 {
					snps,dcb-algorithm;
					snps,map-to-dma-channel = <0x4>;
				};
				queue5 {
					snps,dcb-algorithm;
					snps,map-to-dma-channel = <0x5>;
				};
				queue6 {
					snps,dcb-algorithm;
					snps,map-to-dma-channel = <0x6>;
				};
				queue7 {
					snps,dcb-algorithm;
					snps,map-to-dma-channel = <0x7>;
				};
			};

			mtl_tx_emac0_setup: tx-queues-config {
				snps,tx-queues-to-use = <8>;
				snps,tx-queues-with-coe = <2>;
				snps,tx-sched-wrr;
				queue0 {
					snps,weight = <0x09>;
					snps,dcb-algorithm;
				};
				queue1 {
					snps,weight = <0x0A>;
					snps,dcb-algorithm;
				};
				queue2 {
					snps,weight = <0x0B>;
					snps,dcb-algorithm;
				};
				queue3 {
					snps,weight = <0x0C>;
					snps,dcb-algorithm;
				};
				queue4 {
					snps,weight = <0x0D>;
					snps,dcb-algorithm;
				};
				queue5 {
					snps,weight = <0x0E>;
					snps,dcb-algorithm;
				};
				queue6 {
					snps,weight = <0x0F>;
					snps,dcb-algorithm;
					snps,tbs-enable;
				};
				queue7 {
					snps,weight = <0x10>;
					snps,dcb-algorithm;
					snps,tbs-enable;
				};
			};
		};

		gmac1: ethernet@10820000 {
			compatible = "altr,socfpga-stmmac-a10-s10",
				     "snps,dwxgmac-2.10",
				     "snps,dwxgmac";
			reg = <0x10820000 0x3500>;
			interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "macirq",
					  "macirq_tx0",
					  "macirq_tx1",
					  "macirq_tx2",
					  "macirq_tx3",
					  "macirq_tx4",
					  "macirq_tx5",
					  "macirq_tx6",
					  "macirq_tx7",
					  "macirq_rx0",
					  "macirq_rx1",
					  "macirq_rx2",
					  "macirq_rx3",
					  "macirq_rx4",
					  "macirq_rx5",
					  "macirq_rx6",
					  "macirq_rx7";
			resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
			reset-names = "stmmaceth", "stmmaceth-ocp";
			clocks = <&clkmgr AGILEX5_EMAC1_CLK>,
				 <&clkmgr AGILEX5_EMAC_PTP_CLK>;
			clock-names = "stmmaceth", "ptp_ref";
			mac-address = [00 00 00 00 00 00];
			tx-fifo-depth = <32768>;
			rx-fifo-depth = <16384>;
			snps,multicast-filter-bins = <64>;
			snps,perfect-filter-entries = <64>;
			snps,axi-config = <&stmmac_axi_emac1_setup>;
			snps,mtl-rx-config = <&mtl_rx_emac1_setup>;
			snps,mtl-tx-config = <&mtl_tx_emac1_setup>;
			snps,pbl = <32>;
			snps,pblx8;
			snps,multi-irq-en;
			snps,tso;
			snps,rx-vlan-offload;
			altr,sysmgr-syscon = <&sysmgr 0x48 0>;
			altr,smtg-hub;
			iommus = <&smmu 2>;

			status = "disabled";

			stmmac_axi_emac1_setup: stmmac-axi-config {
				snps,wr_osr_lmt = <31>;
				snps,rd_osr_lmt = <31>;
				snps,blen = <0 0 0 32 16 8 4>;
			};

			mtl_rx_emac1_setup: rx-queues-config {
				snps,rx-queues-to-use = <8>;
				snps,rx-sched-sp;
				queue0 {
					snps,dcb-algorithm;
					snps,map-to-dma-channel = <0x0>;
				};
				queue1 {
					snps,dcb-algorithm;
					snps,map-to-dma-channel = <0x1>;
				};
				queue2 {
					snps,dcb-algorithm;
					snps,map-to-dma-channel = <0x2>;
				};
				queue3 {
					snps,dcb-algorithm;
					snps,map-to-dma-channel = <0x3>;
				};
				queue4 {
					snps,dcb-algorithm;
					snps,map-to-dma-channel = <0x4>;
				};
				queue5 {
					snps,dcb-algorithm;
					snps,map-to-dma-channel = <0x5>;
				};
				queue6 {
					snps,dcb-algorithm;
					snps,map-to-dma-channel = <0x6>;
				};
				queue7 {
					snps,dcb-algorithm;
					snps,map-to-dma-channel = <0x7>;
				};
			};

			mtl_tx_emac1_setup: tx-queues-config {
				snps,tx-queues-to-use = <8>;
				snps,tx-queues-with-coe = <2>;
				snps,tx-sched-wrr;
				queue0 {
					snps,weight = <0x09>;
					snps,dcb-algorithm;
				};
				queue1 {
					snps,weight = <0x0A>;
					snps,dcb-algorithm;
				};
				queue2 {
					snps,weight = <0x0B>;
					snps,dcb-algorithm;
				};
				queue3 {
					snps,weight = <0x0C>;
					snps,dcb-algorithm;
				};
				queue4 {
					snps,weight = <0x0D>;
					snps,dcb-algorithm;
				};
				queue5 {
					snps,weight = <0x0E>;
					snps,dcb-algorithm;
				};
				queue6 {
					snps,weight = <0x0F>;
					snps,dcb-algorithm;
					snps,tbs-enable;
				};
				queue7 {
					snps,weight = <0x10>;
					snps,dcb-algorithm;
					snps,tbs-enable;
				};
			};
		};

		gmac2: ethernet@10830000 {
			compatible = "altr,socfpga-stmmac-a10-s10",
				     "snps,dwxgmac-2.10",
				     "snps,dwxgmac";
			reg = <0x10830000 0x3500>;
			interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "macirq",
					  "macirq_tx0",
					  "macirq_tx1",
					  "macirq_tx2",
					  "macirq_tx3",
					  "macirq_tx4",
					  "macirq_tx5",
					  "macirq_tx6",
					  "macirq_tx7",
					  "macirq_rx0",
					  "macirq_rx1",
					  "macirq_rx2",
					  "macirq_rx3",
					  "macirq_rx4",
					  "macirq_rx5",
					  "macirq_rx6",
					  "macirq_rx7";
			resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
			reset-names = "stmmaceth", "stmmaceth-ocp";
			clocks = <&clkmgr AGILEX5_EMAC2_CLK>,
				 <&clkmgr AGILEX5_EMAC_PTP_CLK>;
			clock-names = "stmmaceth", "ptp_ref";
			mac-address = [00 00 00 00 00 00];
			tx-fifo-depth = <32768>;
			rx-fifo-depth = <16384>;
			snps,multicast-filter-bins = <64>;
			snps,perfect-filter-entries = <64>;
			snps,axi-config = <&stmmac_axi_emac2_setup>;
			snps,mtl-rx-config = <&mtl_rx_emac2_setup>;
			snps,mtl-tx-config = <&mtl_tx_emac2_setup>;
			snps,pbl = <32>;
			snps,pblx8;
			snps,multi-irq-en;
			snps,tso;
			snps,rx-vlan-offload;
			altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
			altr,smtg-hub;
			iommus = <&smmu 3>;

			status = "disabled";

			stmmac_axi_emac2_setup: stmmac-axi-config {
				snps,wr_osr_lmt = <31>;
				snps,rd_osr_lmt = <31>;
				snps,blen = <0 0 0 32 16 8 4>;
			};

			mtl_rx_emac2_setup: rx-queues-config {
				snps,rx-queues-to-use = <8>;
				snps,rx-sched-sp;
				queue0 {
					snps,dcb-algorithm;
					snps,map-to-dma-channel = <0x0>;
				};
				queue1 {
					snps,dcb-algorithm;
					snps,map-to-dma-channel = <0x1>;
				};
				queue2 {
					snps,dcb-algorithm;
					snps,map-to-dma-channel = <0x2>;
				};
				queue3 {
					snps,dcb-algorithm;
					snps,map-to-dma-channel = <0x3>;
				};
				queue4 {
					snps,dcb-algorithm;
					snps,map-to-dma-channel = <0x4>;
				};
				queue5 {
					snps,dcb-algorithm;
					snps,map-to-dma-channel = <0x5>;
				};
				queue6 {
					snps,dcb-algorithm;
					snps,map-to-dma-channel = <0x6>;
				};
				queue7 {
					snps,dcb-algorithm;
					snps,map-to-dma-channel = <0x7>;
				};
			};

			mtl_tx_emac2_setup: tx-queues-config {
				snps,tx-queues-to-use = <8>;
				snps,tx-queues-with-coe = <2>;
				snps,tx-sched-wrr;
				queue0 {
					snps,weight = <0x09>;
					snps,dcb-algorithm;
				};
				queue1 {
					snps,weight = <0x0A>;
					snps,dcb-algorithm;
				};
				queue2 {
					snps,weight = <0x0B>;
					snps,dcb-algorithm;
				};
				queue3 {
					snps,weight = <0x0C>;
					snps,dcb-algorithm;
				};
				queue4 {
					snps,weight = <0x0D>;
					snps,dcb-algorithm;
				};
				queue5 {
					snps,weight = <0x0E>;
					snps,dcb-algorithm;
				};
				queue6 {
					snps,weight = <0x0F>;
					snps,dcb-algorithm;
					snps,tbs-enable;
				};
				queue7 {
					snps,weight = <0x10>;
					snps,dcb-algorithm;
					snps,tbs-enable;
				};
			};
		};

		i2c0: i2c@10c02800 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0x10c02800 0x100>;
			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
			resets = <&rst I2C0_RESET>;
			clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
			status = "disabled";
		};

		i2c1: i2c@10c02900 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0x10c02900 0x100>;
			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
			resets = <&rst I2C1_RESET>;
			clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
			status = "disabled";
		};

		i2c2: i2c@10c02a00 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0x10c02a00 0x100>;
			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
			resets = <&rst I2C2_RESET>;
			clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
			status = "disabled";
		};

		i2c3: i2c@10c02b00 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0x10c02b00 0x100>;
			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
			resets = <&rst I2C3_RESET>;
			clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
			status = "disabled";
		};

		i2c4: i2c@10c02c00 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0x10c02c00 0x100>;
			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
			resets = <&rst I2C4_RESET>;
			clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
			status = "disabled";
		};

		i3c0: i3c@10da0000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,dw-i3c-master-1.00a";
			reg = <0x10da0000 0x1000>;
			interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
			resets = <&rst I3C0_RESET>;
			clocks = <&clkmgr AGILEX5_L4_MP_CLK>;
			status = "disabled";
		};

		i3c1: i3c@10da1000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,dw-i3c-master-1.00a";
			reg = <0x10da1000 0x1000>;
			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
			resets = <&rst I3C1_RESET>;
			clocks = <&clkmgr AGILEX5_L4_MP_CLK>;
			status = "disabled";
		};

		gpio0: gpio@10c03200 {
			compatible = "snps,dw-apb-gpio";
			reg = <0x10c03200 0x100>;
			#address-cells = <1>;
			#size-cells = <0>;
			resets = <&rst GPIO0_RESET>;
			status = "disabled";

			porta: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				reg = <0>;
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <24>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		gpio1: gpio@10C03300 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,dw-apb-gpio";
			reg = <0x10C03300 0x100>;
			resets = <&rst GPIO1_RESET>;
			status = "disabled";

			portb: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <24>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		mmc: mmc0@10808000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "intel,agilex5-sd4hc", "cdns,sd4hc";
			reg = <0x10808000 0x1000>;
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
			fifo-depth = <0x800>;
			resets = <&rst SDMMC_RESET>;
			reset-names = "reset";
			clocks = <&clkmgr AGILEX5_L4_MP_CLK>, <&clkmgr AGILEX5_SDMCLK>;
			clock-names = "biu", "ciu";
			iommus = <&smmu 5>;
			status = "disabled";
		};

		nand: nand-controller@10b80000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "cdns,hp-nfc";
			reg = <0x10b80000 0x10000>,
					<0x10840000 0x1000>;
			reg-names = "reg", "sdma";
			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clkmgr AGILEX5_NAND_NF_CLK>;
			clock-names = "nf_clk";
			cdns,board-delay-ps = <4830>;
			iommus = <&smmu 4>;
			status = "disabled";
		};

		ocram: sram@00000000 {
			compatible = "mmio-sram";
			reg = <0x00000000 0x80000>;
		};

		dmac0: dma-controller@10DB0000 {
			compatible = "snps,axi-dma-1.01a";
			reg = <0x10DB0000 0x500>;
			clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>,
				 <&clkmgr AGILEX5_L4_MP_CLK>;
			clock-names = "core-clk", "cfgr-clk";
			interrupt-parent = <&intc>;
			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
			#dma-cells = <1>;
			dma-channels = <4>;
			snps,dma-masters = <1>;
			snps,data-width = <3>;
			snps,block-size = <32767 32767 32767 32767>;
			snps,priority = <0 1 2 3>;
			snps,axi-max-burst-len = <8>;
			snps,dma-40-bit-mask;
			iommus = <&smmu 8>;
			status = "okay";
		};

		dmac1: dma-controller@10DC0000 {
			compatible = "snps,axi-dma-1.01a";
			reg = <0x10DC0000 0x500>;
			clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>,
				 <&clkmgr AGILEX5_L4_MP_CLK>;
			clock-names = "core-clk", "cfgr-clk";
			interrupt-parent = <&intc>;
			interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
			#dma-cells = <1>;
			dma-channels = <4>;
			snps,dma-masters = <1>;
			snps,data-width = <3>;
			snps,block-size = <32767 32767 32767 32767>;
			snps,priority = <0 1 2 3>;
			snps,axi-max-burst-len = <8>;
			snps,dma-40-bit-mask;
			iommus = <&smmu 9>;
			status = "okay";
		};

		rst: rstmgr@10d11000 {
			#reset-cells = <1>;
			compatible = "altr,stratix10-rst-mgr";
			reg = <0x10d11000 0x100>;
		};

		smmu: iommu@16000000 {
			compatible = "arm,smmu-v3";
			reg = <0x16000000 0x30000>;
			interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "eventq", "gerror", "priq";
			dma-coherent;
			#iommu-cells = <1>;
			status = "disabled";
		};

		spi0: spi@10da4000 {
			compatible = "snps,dw-apb-ssi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x10da4000 0x1000>;
			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
			resets = <&rst SPIM0_RESET>;
			reset-names = "spi";
			reg-io-width = <4>;
			num-cs = <4>;
			clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>;
			dmas = <&dmac0 16>, <&dmac0 17>;
			dma-names ="tx", "rx";
			status = "disabled";
		};

		spi1: spi@10da5000 {
			compatible = "snps,dw-apb-ssi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x10da5000 0x1000>;
			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
			resets = <&rst SPIM1_RESET>;
			reset-names = "spi";
			reg-io-width = <4>;
			num-cs = <4>;
			clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>;
			dmas = <&dmac0 20>, <&dmac0 21>;
			dma-names ="tx", "rx";
			status = "disabled";
		};

		sysmgr: sysmgr@10d12000 {
			compatible = "altr,sys-mgr-s10","altr,sys-mgr";
			reg = <0x10d12000 0x500>;
		};

		timer0: timer0@10c03000 {
			compatible = "snps,dw-apb-timer";
			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x10c03000 0x100>;
			clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
			clock-names = "timer";
		};

		timer1: timer1@10c03100 {
			compatible = "snps,dw-apb-timer";
			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x10c03100 0x100>;
			clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
			clock-names = "timer";
		};

		timer2: timer2@10d00000 {
			compatible = "snps,dw-apb-timer";
			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x10d00000 0x100>;
			clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
			clock-names = "timer";
		};

		timer3: timer3@10d00100 {
			compatible = "snps,dw-apb-timer";
			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x10d00100 0x100>;
			clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
			clock-names = "timer";
		};

		uart0: serial@10c02000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x10c02000 0x100>;
			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			resets = <&rst UART0_RESET>;
			status = "disabled";
			clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
		};

		uart1: serial@10c02100 {
			compatible = "snps,dw-apb-uart";
			reg = <0x10c02100 0x100>;
			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			resets = <&rst UART1_RESET>;
			status = "disabled";
			clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
		};

		usb0: usb@10b00000 {
			compatible = "snps,dwc2";
			reg = <0x10b00000 0x40000>;
			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
			phys = <&usbphy0>;
			phy-names = "usb2-phy";
			resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
			reset-names = "dwc2", "dwc2-ecc";
			clocks = <&clkmgr AGILEX5_USB2OTG_HCLK>;
			clock-names = "otg";
			iommus = <&smmu 6>;
			status = "disabled";
		};

		usb31: usb1@11000000 {
			compatible = "intel,agilex5-dwc3";
			reg = <0x11000000 0x100000>;
			ranges;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&clkmgr AGILEX5_USB31_SUSPEND_CLK>,
				 <&clkmgr AGILEX5_USB31_BUS_CLK_EARLY>;
			resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
			reset-names = "dwc3", "dwc3-ecc";
			status = "disabled";

			dwc3_0: usb@11000000{
				compatible = "snps,dwc3";
				reg = <0x11000000 0x100000>;
				interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
				iommus = <&smmu 7>;
				phys = <&usbphy0>, <&usbphy0>;
				phy-names = "usb2-phy", "usb3-phy";
				maximum-speed = "super-speed-plus";
				snps,dis_u2_sysphy-quirk;
				snps,dma_set_40_bit_mask_quirk;
			};
		};

		eccmgr {
			compatible = "altr,socfpga-a10-ecc-manager";
			altr,sysmgr-syscon = <&sysmgr>;
			#address-cells = <1>;
			#size-cells = <1>;
			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 95 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 120 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "global_sbe", "io96b0" , "io96b1",
					  "sdm_qspi_sbe", "sdm_qspi_dbe", "sdm_seu";
			interrupt-controller;
			#interrupt-cells = <2>;
			ranges;

			ocram-ecc@108cc000 {
				compatible = "altr,socfpga-a10-ocram-ecc";
				reg = <0x108cc000 0x100>;
				interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
			};

			usb0-ecc@108c4000 {
				compatible = "altr,socfpga-usb-ecc";
				reg = <0x108c4000 0x100>;
				altr,ecc-parent = <&usb0>;
				interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
			};

			tsn0-rx-ecc@108c0000 {
				compatible = "altr,socfpga-eth-mac-ecc";
				reg = <0x108c0000 0x100>;
				altr,ecc-parent = <&gmac0>;
				interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
			};

			tsn0-tx-ecc@108c0400 {
				compatible = "altr,socfpga-eth-mac-ecc";
				reg = <0x108c0400 0x100>;
				altr,ecc-parent = <&gmac0>;
				interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
			};

			tsn1-rx-ecc@108c0800 {
				compatible = "altr,socfpga-eth-mac-ecc";
				reg = <0x108c0800 0x100>;
				altr,ecc-parent = <&gmac1>;
				interrupts = <6 IRQ_TYPE_LEVEL_HIGH>;
			};

			tsn1-tx-ecc@108c0C00 {
				compatible = "altr,socfpga-eth-mac-ecc";
				reg = <0x108c0C00 0x100>;
				altr,ecc-parent = <&gmac1>;
				interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
			};

			tsn2-rx-ecc@108c1000 {
				compatible = "altr,socfpga-eth-mac-ecc";
				reg = <0x108c1000 0x100>;
				altr,ecc-parent = <&gmac2>;
				interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
			};

			tsn2-tx-ecc@108c1400 {
				compatible = "altr,socfpga-eth-mac-ecc";
				reg = <0x108c1400 0x100>;
				altr,ecc-parent = <&gmac2>;
				interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
			};

			usb31-ram0-ecc@108c4C00 {
				compatible = "altr,socfpga-usb-ecc";
				reg = <0x108c4C00 0x100>;
				altr,ecc-parent = <&usb31>;
				interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
			};

			usb31-ram1-ecc@108c4800 {
				compatible = "altr,socfpga-usb-ecc";
				reg = <0x108c4800 0x100>;
				altr,ecc-parent = <&usb31>;
				interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
			};

			usb31-ram2-ecc@108c4400 {
				compatible = "altr,socfpga-usb-ecc";
				reg = <0x108c4400 0x100>;
				altr,ecc-parent = <&usb31>;
				interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
			};

			io96b0-ecc {
				compatible = "altr,socfpga-io96b-ecc";
				reg = <0x18400000 0x1000>;
				interrupts = <95 IRQ_TYPE_EDGE_RISING>;
				status = "disabled";
			};

			io96b1-ecc {
				compatible = "altr,socfpga-io96b-ecc";
				reg = <0x18800000 0x1000>;
				interrupts = <120 IRQ_TYPE_EDGE_RISING>;
				status = "disabled";
			};

			sdm-qspi-ecc@10a22000 {
				compatible = "altr,socfpga-sdm-qspi-ecc";
				reg = <0x10a22000 0x100>;
				interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
			};

			cram-seu@0 {
				compatible = "altr,socfpga-cram-seu";
				reg = <0x0 0x0>;
			};
		};

		watchdog0: watchdog@10d00200 {
			compatible = "snps,dw-wdt";
			reg = <0x10d00200 0x100>;
			interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
			resets = <&rst WATCHDOG0_RESET>;
			clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
			status = "disabled";
		};

		watchdog1: watchdog@10d00300 {
			compatible = "snps,dw-wdt";
			reg = <0x10d00300 0x100>;
			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
			resets = <&rst WATCHDOG1_RESET>;
			clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
			status = "disabled";
		};

		watchdog2: watchdog@10d00400 {
			compatible = "snps,dw-wdt";
			reg = <0x10d00400 0x100>;
			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
			resets = <&rst WATCHDOG2_RESET>;
			clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
			status = "disabled";
		};

		watchdog3: watchdog@10d00500 {
			compatible = "snps,dw-wdt";
			reg = <0x10d00500 0x100>;
			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
			resets = <&rst WATCHDOG3_RESET>;
			clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
			status = "disabled";
		};
		watchdog4: watchdog@10d00600 {
			compatible = "snps,dw-wdt";
			reg = <0x10d00600 0x100>;
			interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
			resets = <&rst WATCHDOG4_RESET>;
			clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
			status = "disabled";
		};

		qspi: spi@108d2000 {
			compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x108d2000 0x100>,
			      <0x10900000 0x100000>;
			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
			cdns,fifo-depth = <128>;
			cdns,fifo-width = <4>;
			cdns,trigger-address = <0x00000000>;
			clocks = <&qspi_clk>;
			status = "disabled";
		};

		firmware {
			svc {
				compatible = "intel,agilex5-svc";
				method = "smc";
				memory-region = <&service_reserved>;
				iommus = <&smmu 10>;
				altr,smmu_enable_quirk;

				fpga_mgr: fpga-mgr {
					compatible = "intel,agilex5-soc-fpga-mgr";
				};

				fcs: fcs {
					compatible = "intel,agilex-soc-fcs";
					platform = "agilex";
				};

				temp_volt: hwmon {
					compatible = "intel,soc64-hwmon";
				};
			};
		};
	};
};

 

Many thanks,

K

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Sparrow_Altera
Employee
‎06-17-2025 11:40 AM
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Solved Jump to solution

Thanks for sharing your Agilex 5 .dtsi file. The EMAC (gmac0/gmac1/gmac2) sections look well-defined, however, all three EMACs have status = "disabled";, so the kernel will not load drivers for them unless another .dts or .dtsi file (like a board-specific one) overrides this with status = "okay".

Example for gmac0:

&gmac0 {

    status = "okay";

    phy-mode = "rgmii"; // or "sgmii", "rmii" — depending on your design

    phy-handle = <&phy0>; // reference to an external PHY if used

    // Optional: fixed-link if no external PHY

    fixed-link {

        speed = <1000>;

        full-duplex;

    };

};

Make sure to also define &phy0 if you're using an external PHY. Confirm your boot .dtb includes a version of the EMAC node with status = "okay". Ensure clocks and reset lines are properly asserted and enabled by the bootloader or preloader stage.

The error message that you shared suggests that the DMA controller inside the EMAC IP block isn't initializing properly, likely because its reset line isn't working or hasn't been deasserted.

Couple of things to try:

Check the rst node is working

  • Make sure the reset controller in your .dtsi is active and matches the hardware
  • Ensure your kernel has altr,stratix10-rst-mgr driver enabled
  • Check whether the IDs like EMAC0_RESET are correct (from altr,rst-mgr-agilex5.h)

 

Try without reset control (for debugging)

  • Temporarily, remove the reset lines in the EMAC node to test if the problem is reset-controller-related -> If EMAC initializes without errors afterward, then the issue is definitely the reset controller.

 

Ensure EMAC is powered and clocked

  • Even if resets are correct, clocks must be enabled
  • Make sure, Clock controller (clkmgr) is active and functional
  • These clocks are not gated or unconfigured by U-Boot or preloader - Use U-Boot to verify clock settings, or explicitly enable the clocks in bootloader

 

Enable only one EMAC first

  • Only bring up gmac0 initially. In your board .dts

&gmac0 {

    status = "okay";

    phy-mode = "sgmii"; // or your actual mode

    fixed-link {

        speed = <1000>;

        full-duplex;

    };

};

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MattG_Altera
Employee
‎06-17-2025 12:15 PM
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Solved Jump to solution

From Linux, you can get summary of the state of the clock tree with the following command:

 cat /sys/kernel/debug/clk/clk_summary

 

 

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K606
New Contributor III
‎06-18-2025 01:43 AM
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Solved Jump to solution
In response to MattG_Altera

Hi Matt - yes for sure here is the dump:

root@localhost:~# cat /sys/kernel/debug/clk/clk_summary
                                 enable  prepare  protect                                duty  hardware
   clock                          count    count    count        rate   accuracy phase  cycle    enable
-------------------------------------------------------------------------------------------------------
 qspi-clk                             1        1        0   200000000          0     0  50000         Y
 osc1                                 2        2        0    25000000          0     0  50000         Y
    periph_pll                        1        1        0  2500000000          0     0  50000         Y
       peri_pll_c3                    1        1        0   500000000          0     0  50000         Y
          psi_ref_free_clk            0        0        0   500000000          0     0  50000         Y
             psi_ref_clk              0        0        0   500000000          0     0  50000         Y
          s2f_user1_free_clk          0        0        0   500000000          0     0  50000         Y
             s2f_user1_clk            0        0        0   500000000          0     0  50000         Y
          s2f_user0_free_clk          0        0        0   500000000          0     0  50000         Y
             s2f_user0_clk            0        0        0   500000000          0     0  50000         Y
          emaca_free_clk              1        1        0   250000000          0     0  50000         Y
             emac2_clk                1        1        0   250000000          0     0  50000         Y
             emac1_clk                0        0        0   250000000          0     0  50000         Y
             emac0_clk                0        0        0   250000000          0     0  50000         Y
       peri_pll_c2                    0        0        0    25000000          0     0  50000         Y
       peri_pll_c1                    0        0        0   500000000          0     0  50000         Y
       peri_pll_c0                    0        0        0  1250000000          0     0  50000         Y
          dsu_free_clk                0        0        0  1250000000          0     0  50000         Y
             mpu_ccu_clk              0        0        0   625000000          0     0  50000         Y
             mpu_periph_clk           0        0        0   312500000          0     0  50000         Y
             dsu_clk                  0        0        0  1250000000          0     0  50000         Y
    main_pll                          1        1        0  2800000000          0     0  50000         Y
       main_pll_c3                    3        3        0   400000000          0     0  50000         Y
          usb31_free_clk              1        1        0    20000000          0     0  50000         Y
             usb31_suspend_clk        1        1        0    20000000          0     0  50000         Y
          gpio_db_free_clk            0        0        0   200000000          0     0  50000         Y
             gpio_db_clk              0        0        0   200000000          0     0  50000         Y
          emac_ptp_free_clk           1        1        0   400000000          0     0  50000         Y
             emac_ptp_clk             1        1        0   400000000          0     0  50000         Y
          noc_free_clk                4        4        0   400000000          0     0  50000         Y
             cs_trace_clk             0        0        0   100000000          0     0  50000         Y
             cs_at_clk                0        0        0   400000000          0     0  50000         Y
                cs_pdbg_clk           0        0        0   100000000          0     0  50000         Y
             l4_sp_clk                2        2        0   100000000          0     0  50000         Y
                sptimer_1_pclk        0        0        0   100000000          0     0  50000         Y
                sptimer_0_pclk        0        0        0   100000000          0     0  50000         Y
                uart_1_pclk           0        0        0   100000000          0     0  50000         Y
                uart_0_pclk           0        0        0   100000000          0     0  50000         Y
                i2c_emac2_pclk        0        0        0   100000000          0     0  50000         Y
                i2c_emac1_pclk        0        0        0   100000000          0     0  50000         Y
                i2c_emac0_pclk        0        0        0   100000000          0     0  50000         Y
                i2c_1_pclk            0        0        0   100000000          0     0  50000         Y
                i2c_0_pclk            0        0        0   100000000          0     0  50000         Y
                spis_1_clk            0        0        0   100000000          0     0  50000         Y
                spis_0_clk            0        0        0   100000000          0     0  50000         Y
             l4_sys_free_clk          5        5        0   100000000          0     0  50000         Y
             l4_mp_clk                1        1        0   200000000          0     0  50000         Y
                softphy_phy_clk       0        0        0   200000000          0     0  50000         Y
                softphy_reg_pclk       0        0        0   200000000          0     0  50000         Y
                sdmmc_sdphy_reg_clk       0        0        0   200000000          0     0  50000         Y
                nand_bch_clk          0        0        0   200000000          0     0  50000         Y
                dfi_clk               0        0        0   200000000          0     0  50000         Y
                   softphy_ctrl_clk       0        0        0   200000000          0     0  50000         Y
                   sdmclk             0        0        0   200000000          0     0  50000         Y
                   nand_nf_clk        0        0        0   200000000          0     0  50000         Y
                i3c_1_core_clk        0        0        0   200000000          0     0  50000         Y
                i3c_0_core_clk        0        0        0   200000000          0     0  50000         Y
                dma_hs_clk            0        0        0   200000000          0     0  50000         Y
                dma_core_clk          0        0        0   200000000          0     0  50000         Y
                spim_1_clk            0        0        0   200000000          0     0  50000         Y
                spim_0_clk            0        0        0   200000000          0     0  50000         Y
                usb2otg_hclk          0        0        0   200000000          0     0  50000         Y
             l4_main_clk              1        1        0   400000000          0     0  50000         Y
                usb31_bus_clk_early       1        1        0   400000000          0     0  50000         Y
       main_pll_c2                    0        0        0   933333333          0     0  50000         Y
       main_pll_c1                    0        0        0   700000000          0     0  50000         Y
          emacb_free_clk              0        0        0    70000000          0     0  50000         Y
          core1_free_clk              0        0        0   700000000          0     0  50000         Y
             core1_clk                0        0        0   700000000          0     0  50000         Y
          core0_free_clk              0        0        0   700000000          0     0  50000         Y
             core0_clk                0        0        0   700000000          0     0  50000         Y
       main_pll_c0                    0        0        0  1400000000          0     0  50000         Y
          core3_free_clk              0        0        0  1400000000          0     0  50000         Y
             core3_clk                0        0        0  1400000000          0     0  50000         Y
          core2_free_clk              0        0        0  1400000000          0     0  50000         Y
             core2_clk                0        0        0  1400000000          0     0  50000         Y
    boot_clk

 

In addition, when the device tree is configured as:

&gmac0 {
	status = "okay";
	mac-mode = "gmii";
	phy-mode = "gmii";
	fixed-link {
		speed = <1000>;
		full-duplex;
	};
};

&gmac1 {
	status = "okay";
	mac-mode = "gmii";
	phy-mode = "gmii";
	fixed-link {
		speed = <1000>;
		full-duplex;
	};
};

 Then the dump is:

 

root@localhost:~# cat /sys/kernel/debug/clk/clk_summary
                                 enable  prepare  protect                                duty  hardware
   clock                          count    count    count        rate   accuracy phase  cycle    enable
-------------------------------------------------------------------------------------------------------
 qspi-clk                             1        1        0   200000000          0     0  50000         Y
 osc1                                 2        2        0    25000000          0     0  50000         Y
    periph_pll                        1        1        0  2500000000          0     0  50000         Y
       peri_pll_c3                    1        1        0   500000000          0     0  50000         Y
          psi_ref_free_clk            0        0        0   500000000          0     0  50000         Y
             psi_ref_clk              0        0        0   500000000          0     0  50000         Y
          s2f_user1_free_clk          0        0        0   500000000          0     0  50000         Y
             s2f_user1_clk            0        0        0   500000000          0     0  50000         Y
          s2f_user0_free_clk          0        0        0   500000000          0     0  50000         Y
             s2f_user0_clk            0        0        0   500000000          0     0  50000         Y
          emaca_free_clk              1        1        0   250000000          0     0  50000         Y
             emac2_clk                1        1        0   250000000          0     0  50000         Y
             emac1_clk                0        0        0   250000000          0     0  50000         Y
             emac0_clk                0        0        0   250000000          0     0  50000         Y
       peri_pll_c2                    0        0        0    25000000          0     0  50000         Y
       peri_pll_c1                    0        0        0   500000000          0     0  50000         Y
       peri_pll_c0                    0        0        0  1250000000          0     0  50000         Y
          dsu_free_clk                0        0        0  1250000000          0     0  50000         Y
             mpu_ccu_clk              0        0        0   625000000          0     0  50000         Y
             mpu_periph_clk           0        0        0   312500000          0     0  50000         Y
             dsu_clk                  0        0        0  1250000000          0     0  50000         Y
    main_pll                          1        1        0  2800000000          0     0  50000         Y
       main_pll_c3                    3        3        0   400000000          0     0  50000         Y
          usb31_free_clk              1        1        0    20000000          0     0  50000         Y
             usb31_suspend_clk        1        1        0    20000000          0     0  50000         Y
          gpio_db_free_clk            0        0        0   200000000          0     0  50000         Y
             gpio_db_clk              0        0        0   200000000          0     0  50000         Y
          emac_ptp_free_clk           1        1        0   400000000          0     0  50000         Y
             emac_ptp_clk             1        1        0   400000000          0     0  50000         Y
          noc_free_clk                4        4        0   400000000          0     0  50000         Y
             cs_trace_clk             0        0        0   100000000          0     0  50000         Y
             cs_at_clk                0        0        0   400000000          0     0  50000         Y
                cs_pdbg_clk           0        0        0   100000000          0     0  50000         Y
             l4_sp_clk                2        2        0   100000000          0     0  50000         Y
                sptimer_1_pclk        0        0        0   100000000          0     0  50000         Y
                sptimer_0_pclk        0        0        0   100000000          0     0  50000         Y
                uart_1_pclk           0        0        0   100000000          0     0  50000         Y
                uart_0_pclk           0        0        0   100000000          0     0  50000         Y
                i2c_emac2_pclk        0        0        0   100000000          0     0  50000         Y
                i2c_emac1_pclk        0        0        0   100000000          0     0  50000         Y
                i2c_emac0_pclk        0        0        0   100000000          0     0  50000         Y
                i2c_1_pclk            0        0        0   100000000          0     0  50000         Y
                i2c_0_pclk            0        0        0   100000000          0     0  50000         Y
                spis_1_clk            0        0        0   100000000          0     0  50000         Y
                spis_0_clk            0        0        0   100000000          0     0  50000         Y
             l4_sys_free_clk          5        5        0   100000000          0     0  50000         Y
             l4_mp_clk                1        1        0   200000000          0     0  50000         Y
                softphy_phy_clk       0        0        0   200000000          0     0  50000         Y
                softphy_reg_pclk       0        0        0   200000000          0     0  50000         Y
                sdmmc_sdphy_reg_clk       0        0        0   200000000          0     0  50000         Y
                nand_bch_clk          0        0        0   200000000          0     0  50000         Y
                dfi_clk               0        0        0   200000000          0     0  50000         Y
                   softphy_ctrl_clk       0        0        0   200000000          0     0  50000         Y
                   sdmclk             0        0        0   200000000          0     0  50000         Y
                   nand_nf_clk        0        0        0   200000000          0     0  50000         Y
                i3c_1_core_clk        0        0        0   200000000          0     0  50000         Y
                i3c_0_core_clk        0        0        0   200000000          0     0  50000         Y
                dma_hs_clk            0        0        0   200000000          0     0  50000         Y
                dma_core_clk          0        0        0   200000000          0     0  50000         Y
                spim_1_clk            0        0        0   200000000          0     0  50000         Y
                spim_0_clk            0        0        0   200000000          0     0  50000         Y
                usb2otg_hclk          0        0        0   200000000          0     0  50000         Y
             l4_main_clk              1        1        0   400000000          0     0  50000         Y
                usb31_bus_clk_early       1        1        0   400000000          0     0  50000         Y
       main_pll_c2                    0        0        0   933333333          0     0  50000         Y
       main_pll_c1                    0        0        0   700000000          0     0  50000         Y
          emacb_free_clk              0        0        0    70000000          0     0  50000         Y
          core1_free_clk              0        0        0   700000000          0     0  50000         Y
             core1_clk                0        0        0   700000000          0     0  50000         Y
          core0_free_clk              0        0        0   700000000          0     0  50000         Y
             core0_clk                0        0        0   700000000          0     0  50000         Y
       main_pll_c0                    0        0        0  1400000000          0     0  50000         Y
          core3_free_clk              0        0        0  1400000000          0     0  50000         Y
             core3_clk                0        0        0  1400000000          0     0  50000         Y
          core2_free_clk              0        0        0  1400000000          0     0  50000         Y
             core2_clk                0        0        0  1400000000          0     0  50000         Y
    boot_clk
In response to MattG_Altera
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TiensungA_Altera
Employee
‎06-17-2025 07:19 PM
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On top of what my other colleagues asked,  Can you also dump, the boot Linux log for all the lines that mentions "socfpga-dwmac"?

I want to understand if the Hard IP is even accessible or enabled correctly by the Quartus design for Ethernet. The example i have here is for gmac2. But you are using gmac0 and gmac1. It seems you are unable to even perform the initial setup of the ETH HW which has a DMA engine. This requires write to the ETH HW CSR register address. 

I want to see if the GMAC0 and GMAC1 are even enabled correctly from the Quartus design at the HPS. 

In the Quartus HPS config, did you enable GMAC0 and GMAC1 from the dropdowns to select the function? 

GMAC0: → [ RGMII ] / [ SGMII ] / [ Disabled ]
GMAC1: → [ RGMII ] / [ SGMII ] / [ Disabled ]

This should be propagated as a handoff data to the U-boot HPS FSBL which will configure the PINMUX and also CLK settings. The Handoff is important to the HPS to configure the ETH clock settings and pinmux. The GMAC0 and GMAC1 reset should already been de-asserted by the U-boot during boot-up. So, i don't suspect the reset de-assertion. It is either the CLK or the PINMUX or a combination of both. Without CLK, the IP will be permanently be disabled. CLK is the major suspect.

In short, I suspect that, the GMAC0 and GMAC1 CLK are disabled by a bad Quartus configuration.

TiensungA_Altera_0-1750218951226.png

 

Log for Linux: Example for a working GMAC on GMAC2. I need to see the similar log for GMAC0 and GMAC1 on your end. I want to know how far it went before it threw the error.

[    0.744790] socfpga-dwmac 10830000.ethernet: Adding to iommu group 0

[    0.746937] socfpga-dwmac 10830000.ethernet: IRQ eth_wake_irq not found

[    0.747646] socfpga-dwmac 10830000.ethernet: IRQ eth_lpi not found

[    0.748310] socfpga-dwmac 10830000.ethernet: IRQ sfty not found

[    0.749186] socfpga-dwmac 10830000.ethernet: SMTG Hub Cross Timestamp supported

[    0.750124] socfpga-dwmac 10830000.ethernet: User ID: 0x76, Synopsys ID: 0x31

[    0.750897] socfpga-dwmac 10830000.ethernet:         XGMAC2

[    0.751426] socfpga-dwmac 10830000.ethernet: DMA HW capability register supported

[    0.752217] socfpga-dwmac 10830000.ethernet: RX Checksum Offload Engine supported

[    0.753010] socfpga-dwmac 10830000.ethernet: COE Type 1

[    0.753568] socfpga-dwmac 10830000.ethernet: TX Checksum insertion supported

[    0.754310] socfpga-dwmac 10830000.ethernet: TSO supported

[    0.754904] socfpga-dwmac 10830000.ethernet: Enabled L3L4 Flow TC (entries=16)

[    0.755669] socfpga-dwmac 10830000.ethernet: Enabled RFS Flow TC (entries=10)

[    0.756422] socfpga-dwmac 10830000.ethernet: TSO feature enabled

[    0.757061] socfpga-dwmac 10830000.ethernet: SPH feature enabled

[    0.757698] socfpga-dwmac 10830000.ethernet: Using 40/40 bits DMA host/device width

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K606
New Contributor III
‎06-18-2025 01:45 AM
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In response to TiensungA_Altera

Hi Tiensung, thanks for the detailed response. Here is the dump you asked for:

root@localhost:~# dmesg | grep "socfpga-dwmac"
[    1.433914] socfpga-dwmac 10810000.ethernet: Adding to iommu group 0
[    1.440789] socfpga-dwmac 10810000.ethernet: IRQ eth_wake_irq not found
[    1.447387] socfpga-dwmac 10810000.ethernet: IRQ eth_lpi not found
[    1.453610] socfpga-dwmac 10810000.ethernet: RX VLAN HW Stripping
[    1.459766] socfpga-dwmac 10810000.ethernet: SMTG Hub Cross Timestamp supported
[    1.467356] socfpga-dwmac 10810000.ethernet: User ID: 0x76, Synopsys ID: 0x31
[    1.474476] socfpga-dwmac 10810000.ethernet:         XGMAC2
[    1.479421] socfpga-dwmac 10810000.ethernet: DMA HW capability register supported
[    1.486867] socfpga-dwmac 10810000.ethernet: RX Checksum Offload Engine supported
[    1.494311] socfpga-dwmac 10810000.ethernet: COE Type 1
[    1.499510] socfpga-dwmac 10810000.ethernet: TX Checksum insertion supported
[    1.506522] socfpga-dwmac 10810000.ethernet: TSO supported
[    1.511980] socfpga-dwmac 10810000.ethernet: Enable RX Mitigation via HW Watchdog Timer
[    1.519954] socfpga-dwmac 10810000.ethernet: device MAC address ca:3e:cc:fb:1a:6f
[    1.527409] socfpga-dwmac 10810000.ethernet: Enabled L3L4 Flow TC (entries=16)
[    1.534597] socfpga-dwmac 10810000.ethernet: Enabled RFS Flow TC (entries=10)
[    1.541696] socfpga-dwmac 10810000.ethernet: TSO feature enabled
[    1.547672] socfpga-dwmac 10810000.ethernet: SPH feature enabled
[    1.553647] socfpga-dwmac 10810000.ethernet: TX COE limited to 2 tx queues
[    1.560490] socfpga-dwmac 10810000.ethernet: Using 40/40 bits DMA host/device width
[    1.568244] socfpga-dwmac 10810000.ethernet (unnamed net_device) (uninitialized): failed to setup phy (-22)
[    1.578069] socfpga-dwmac: probe of 10810000.ethernet failed with error -22
[    1.585185] socfpga-dwmac 10820000.ethernet: Adding to iommu group 1
[    1.591958] socfpga-dwmac 10820000.ethernet: IRQ eth_wake_irq not found
[    1.598547] socfpga-dwmac 10820000.ethernet: IRQ eth_lpi not found
[    1.604742] socfpga-dwmac 10820000.ethernet: RX VLAN HW Stripping
[    1.610871] socfpga-dwmac 10820000.ethernet: SMTG Hub Cross Timestamp supported
[    1.618262] socfpga-dwmac 10820000.ethernet: User ID: 0x76, Synopsys ID: 0x31
[    1.625371] socfpga-dwmac 10820000.ethernet:         XGMAC2
[    1.630312] socfpga-dwmac 10820000.ethernet: DMA HW capability register supported
[    1.637756] socfpga-dwmac 10820000.ethernet: RX Checksum Offload Engine supported
[    1.645200] socfpga-dwmac 10820000.ethernet: COE Type 1
[    1.650400] socfpga-dwmac 10820000.ethernet: TX Checksum insertion supported
[    1.657412] socfpga-dwmac 10820000.ethernet: TSO supported
[    1.662870] socfpga-dwmac 10820000.ethernet: Enable RX Mitigation via HW Watchdog Timer
[    1.670837] socfpga-dwmac 10820000.ethernet: device MAC address 9a:56:d9:98:64:37
[    1.678288] socfpga-dwmac 10820000.ethernet: Enabled L3L4 Flow TC (entries=16)
[    1.685476] socfpga-dwmac 10820000.ethernet: Enabled RFS Flow TC (entries=10)
[    1.692576] socfpga-dwmac 10820000.ethernet: TSO feature enabled
[    1.698551] socfpga-dwmac 10820000.ethernet: SPH feature enabled
[    1.704526] socfpga-dwmac 10820000.ethernet: TX COE limited to 2 tx queues
[    1.711367] socfpga-dwmac 10820000.ethernet: Using 40/40 bits DMA host/device width
[    1.719030] socfpga-dwmac 10820000.ethernet (unnamed net_device) (uninitialized): failed to setup phy (-22)
[    1.728811] socfpga-dwmac: probe of 10820000.ethernet failed with error -22
[    1.735813] socfpga-dwmac 10830000.ethernet: Adding to iommu group 2
[    1.742511] socfpga-dwmac 10830000.ethernet: IRQ eth_wake_irq not found
[    1.749095] socfpga-dwmac 10830000.ethernet: IRQ eth_lpi not found
[    1.755277] socfpga-dwmac 10830000.ethernet: RX VLAN HW Stripping
[    1.761389] socfpga-dwmac 10830000.ethernet: SMTG Hub Cross Timestamp supported
[    1.768798] socfpga-dwmac 10830000.ethernet: User ID: 0x76, Synopsys ID: 0x31
[    1.775904] socfpga-dwmac 10830000.ethernet:         XGMAC2
[    1.780844] socfpga-dwmac 10830000.ethernet: DMA HW capability register supported
[    1.788288] socfpga-dwmac 10830000.ethernet: RX Checksum Offload Engine supported
[    1.795732] socfpga-dwmac 10830000.ethernet: COE Type 1
[    1.800930] socfpga-dwmac 10830000.ethernet: TX Checksum insertion supported
[    1.807942] socfpga-dwmac 10830000.ethernet: TSO supported
[    1.813399] socfpga-dwmac 10830000.ethernet: Enable RX Mitigation via HW Watchdog Timer
[    1.821365] socfpga-dwmac 10830000.ethernet: Enabled L3L4 Flow TC (entries=16)
[    1.828554] socfpga-dwmac 10830000.ethernet: Enabled RFS Flow TC (entries=10)
[    1.835654] socfpga-dwmac 10830000.ethernet: TSO feature enabled
[    1.841629] socfpga-dwmac 10830000.ethernet: SPH feature enabled
[    1.847605] socfpga-dwmac 10830000.ethernet: TX COE limited to 2 tx queues
[    1.854445] socfpga-dwmac 10830000.ethernet: Using 40/40 bits DMA host/device width
[    2.448680] socfpga-dwmac 10830000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-0
[    2.457891] socfpga-dwmac 10830000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-1
[    2.467051] socfpga-dwmac 10830000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-2
[    2.476248] socfpga-dwmac 10830000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-3
[    2.485428] socfpga-dwmac 10830000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-4
[    2.494627] socfpga-dwmac 10830000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-5
[    2.503864] socfpga-dwmac 10830000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-6
[    2.513108] socfpga-dwmac 10830000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-7
[    2.589649] socfpga-dwmac 10830000.ethernet eth0: PHY [stmmac-2:01] driver [Micrel KSZ9031 Gigabit PHY] (irq=POLL)
[    2.600063] socfpga-dwmac 10830000.ethernet eth0: No Safety Features support found
[    2.607619] socfpga-dwmac 10830000.ethernet eth0: IEEE 1588-2008 Advanced Timestamp supported
[    2.616428] socfpga-dwmac 10830000.ethernet eth0: registered PTP clock
[    2.623199] socfpga-dwmac 10830000.ethernet eth0: FPE workqueue start
[    2.629622] socfpga-dwmac 10830000.ethernet eth0: configuring for phy/rgmii-id link mode
[    6.724299] socfpga-dwmac 10830000.ethernet eth0: Link is Up - 1Gbps/Full - flow control rx/tx

 

Additionally, here is the EMAC config:

 

Screenshot 2025-06-18 091247.png

Screenshot 2025-06-18 091211.png

Screenshot 2025-06-18 091148.png

Screenshot 2025-06-18 091137.png

Screenshot 2025-06-18 091122.png

 

I had assumed that since I am t using a PHY right now, I don't need to configure the PHY options - but perhaps the PHY needs to be set in either case?

 

Many thanks,

K

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K606
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‎06-18-2025 01:52 AM
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Note also that when using the config:

&gmac0 {
	status = "okay";
	mac-mode = "gmii";
	phy-mode = "gmii";
	fixed-link {
		speed = <1000>;
		full-duplex;
	};
};

&gmac1 {
	status = "okay";
	mac-mode = "gmii";
	phy-mode = "gmii";
	fixed-link {
		speed = <1000>;
		full-duplex;
	};
};

 

The dump is as followed;

root@localhost:~# dmesg | grep "socfpga-dwmac"
[    1.462464] socfpga-dwmac 10810000.ethernet: Adding to iommu group 0
[    1.469523] socfpga-dwmac 10810000.ethernet: IRQ eth_wake_irq not found
[    1.476126] socfpga-dwmac 10810000.ethernet: IRQ eth_lpi not found
[    1.482375] socfpga-dwmac 10810000.ethernet: RX VLAN HW Stripping
[    1.488570] socfpga-dwmac 10810000.ethernet: SMTG Hub Cross Timestamp supported
[    1.496179] socfpga-dwmac 10810000.ethernet: User ID: 0x76, Synopsys ID: 0x31
[    1.503306] socfpga-dwmac 10810000.ethernet:         XGMAC2
[    1.508265] socfpga-dwmac 10810000.ethernet: DMA HW capability register supported
[    1.515722] socfpga-dwmac 10810000.ethernet: RX Checksum Offload Engine supported
[    1.523175] socfpga-dwmac 10810000.ethernet: COE Type 1
[    1.528381] socfpga-dwmac 10810000.ethernet: TX Checksum insertion supported
[    1.535400] socfpga-dwmac 10810000.ethernet: TSO supported
[    1.540864] socfpga-dwmac 10810000.ethernet: Enable RX Mitigation via HW Watchdog Timer
[    1.548853] socfpga-dwmac 10810000.ethernet: device MAC address de:c4:c9:3e:39:39
[    1.556319] socfpga-dwmac 10810000.ethernet: Enabled L3L4 Flow TC (entries=16)
[    1.563515] socfpga-dwmac 10810000.ethernet: Enabled RFS Flow TC (entries=10)
[    1.570624] socfpga-dwmac 10810000.ethernet: TSO feature enabled
[    1.576607] socfpga-dwmac 10810000.ethernet: SPH feature enabled
[    1.582590] socfpga-dwmac 10810000.ethernet: TX COE limited to 2 tx queues
[    1.589441] socfpga-dwmac 10810000.ethernet: Using 40/40 bits DMA host/device width
[    1.598267] socfpga-dwmac 10820000.ethernet: Adding to iommu group 1
[    1.605275] socfpga-dwmac 10820000.ethernet: IRQ eth_wake_irq not found
[    1.611882] socfpga-dwmac 10820000.ethernet: IRQ eth_lpi not found
[    1.618112] socfpga-dwmac 10820000.ethernet: RX VLAN HW Stripping
[    1.624296] socfpga-dwmac 10820000.ethernet: SMTG Hub Cross Timestamp supported
[    1.631762] socfpga-dwmac 10820000.ethernet: User ID: 0x76, Synopsys ID: 0x31
[    1.638884] socfpga-dwmac 10820000.ethernet:         XGMAC2
[    1.643838] socfpga-dwmac 10820000.ethernet: DMA HW capability register supported
[    1.651292] socfpga-dwmac 10820000.ethernet: RX Checksum Offload Engine supported
[    1.658748] socfpga-dwmac 10820000.ethernet: COE Type 1
[    1.663955] socfpga-dwmac 10820000.ethernet: TX Checksum insertion supported
[    1.670976] socfpga-dwmac 10820000.ethernet: TSO supported
[    1.676442] socfpga-dwmac 10820000.ethernet: Enable RX Mitigation via HW Watchdog Timer
[    1.684423] socfpga-dwmac 10820000.ethernet: device MAC address 3e:48:9a:b2:60:c6
[    1.691880] socfpga-dwmac 10820000.ethernet: Enabled L3L4 Flow TC (entries=16)
[    1.699074] socfpga-dwmac 10820000.ethernet: Enabled RFS Flow TC (entries=10)
[    1.706184] socfpga-dwmac 10820000.ethernet: TSO feature enabled
[    1.712168] socfpga-dwmac 10820000.ethernet: SPH feature enabled
[    1.718151] socfpga-dwmac 10820000.ethernet: TX COE limited to 2 tx queues
[    1.725000] socfpga-dwmac 10820000.ethernet: Using 40/40 bits DMA host/device width
[    1.733603] socfpga-dwmac 10830000.ethernet: Adding to iommu group 2
[    1.740561] socfpga-dwmac 10830000.ethernet: IRQ eth_wake_irq not found
[    1.747164] socfpga-dwmac 10830000.ethernet: IRQ eth_lpi not found
[    1.753382] socfpga-dwmac 10830000.ethernet: RX VLAN HW Stripping
[    1.759597] socfpga-dwmac 10830000.ethernet: SMTG Hub Cross Timestamp supported
[    1.767082] socfpga-dwmac 10830000.ethernet: User ID: 0x76, Synopsys ID: 0x31
[    1.774210] socfpga-dwmac 10830000.ethernet:         XGMAC2
[    1.779163] socfpga-dwmac 10830000.ethernet: DMA HW capability register supported
[    1.786615] socfpga-dwmac 10830000.ethernet: RX Checksum Offload Engine supported
[    1.794068] socfpga-dwmac 10830000.ethernet: COE Type 1
[    1.799274] socfpga-dwmac 10830000.ethernet: TX Checksum insertion supported
[    1.806294] socfpga-dwmac 10830000.ethernet: TSO supported
[    1.811759] socfpga-dwmac 10830000.ethernet: Enable RX Mitigation via HW Watchdog Timer
[    1.819732] socfpga-dwmac 10830000.ethernet: Enabled L3L4 Flow TC (entries=16)
[    1.826926] socfpga-dwmac 10830000.ethernet: Enabled RFS Flow TC (entries=10)
[    1.834067] socfpga-dwmac 10830000.ethernet: TSO feature enabled
[    1.840053] socfpga-dwmac 10830000.ethernet: SPH feature enabled
[    1.846036] socfpga-dwmac 10830000.ethernet: TX COE limited to 2 tx queues
[    1.852887] socfpga-dwmac 10830000.ethernet: Using 40/40 bits DMA host/device width
[    2.213371] socfpga-dwmac 10810000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-0
[    2.223819] socfpga-dwmac 10810000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-1
[    2.234195] socfpga-dwmac 10810000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-2
[    2.244611] socfpga-dwmac 10810000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-3
[    2.255079] socfpga-dwmac 10810000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-4
[    2.265557] socfpga-dwmac 10810000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-5
[    2.276090] socfpga-dwmac 10810000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-6
[    2.286544] socfpga-dwmac 10810000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-7
[    2.398706] socfpga-dwmac 10810000.ethernet: Failed to reset the dma
[    2.405047] socfpga-dwmac 10810000.ethernet eth0: stmmac_hw_setup: DMA engine initialization failed
[    2.414059] socfpga-dwmac 10810000.ethernet eth0: __stmmac_open: Hw setup failed
[    2.458913] socfpga-dwmac 10820000.ethernet eth1: Register MEM_TYPE_PAGE_POOL RxQ-0
[    2.469006] socfpga-dwmac 10820000.ethernet eth1: Register MEM_TYPE_PAGE_POOL RxQ-1
[    2.479217] socfpga-dwmac 10820000.ethernet eth1: Register MEM_TYPE_PAGE_POOL RxQ-2
[    2.489414] socfpga-dwmac 10820000.ethernet eth1: Register MEM_TYPE_PAGE_POOL RxQ-3
[    2.499697] socfpga-dwmac 10820000.ethernet eth1: Register MEM_TYPE_PAGE_POOL RxQ-4
[    2.510018] socfpga-dwmac 10820000.ethernet eth1: Register MEM_TYPE_PAGE_POOL RxQ-5
[    2.520428] socfpga-dwmac 10820000.ethernet eth1: Register MEM_TYPE_PAGE_POOL RxQ-6
[    2.530730] socfpga-dwmac 10820000.ethernet eth1: Register MEM_TYPE_PAGE_POOL RxQ-7
[    2.642587] socfpga-dwmac 10820000.ethernet: Failed to reset the dma
[    2.648934] socfpga-dwmac 10820000.ethernet eth1: stmmac_hw_setup: DMA engine initialization failed
[    2.657945] socfpga-dwmac 10820000.ethernet eth1: __stmmac_open: Hw setup failed
[    2.702120] socfpga-dwmac 10830000.ethernet eth2: Register MEM_TYPE_PAGE_POOL RxQ-0
[    2.712182] socfpga-dwmac 10830000.ethernet eth2: Register MEM_TYPE_PAGE_POOL RxQ-1
[    2.722405] socfpga-dwmac 10830000.ethernet eth2: Register MEM_TYPE_PAGE_POOL RxQ-2
[    2.732655] socfpga-dwmac 10830000.ethernet eth2: Register MEM_TYPE_PAGE_POOL RxQ-3
[    2.742905] socfpga-dwmac 10830000.ethernet eth2: Register MEM_TYPE_PAGE_POOL RxQ-4
[    2.753211] socfpga-dwmac 10830000.ethernet eth2: Register MEM_TYPE_PAGE_POOL RxQ-5
[    2.763547] socfpga-dwmac 10830000.ethernet eth2: Register MEM_TYPE_PAGE_POOL RxQ-6
[    2.773952] socfpga-dwmac 10830000.ethernet eth2: Register MEM_TYPE_PAGE_POOL RxQ-7
[    2.853772] socfpga-dwmac 10830000.ethernet eth2: PHY [stmmac-2:01] driver [Micrel KSZ9031 Gigabit PHY] (irq=POLL)
[    2.864173] socfpga-dwmac 10830000.ethernet eth2: No Safety Features support found
[    2.871745] socfpga-dwmac 10830000.ethernet eth2: IEEE 1588-2008 Advanced Timestamp supported
[    2.880564] socfpga-dwmac 10830000.ethernet eth2: registered PTP clock
[    2.887436] socfpga-dwmac 10830000.ethernet eth2: FPE workqueue start
[    2.893868] socfpga-dwmac 10830000.ethernet eth2: configuring for phy/rgmii-id link mode
[    6.980275] socfpga-dwmac 10830000.ethernet eth2: Link is Up - 1Gbps/Full - flow control rx/tx
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Sparrow_Altera
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‎06-18-2025 02:16 PM
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The fact that gmac2 works, while gmac0/gmac1 fail with identical setup, strongly suggests-> The reset lines for EMAC0 and EMAC1 are not wired or released correctly in the FPGA handoff.

The Linux kernel attempts to reset the DMA via

resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;

But these don't actually trigger a reset, leave the DMA in a bad state.

Try a simple test, comment out the resets for gmac0:

// resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;

                 // reset-names = "stmmaceth", "stmmaceth-ocp";

Recompile and reboot. If this makes the error go away (or lets the DMA at least initialize), the reset was the issue.

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K606
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‎06-23-2025 06:54 AM
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In response to Sparrow_Altera

Thanks for this suggestion! However it seems that this does not solve the issue. I would be interested to see the rest of the snippet you shared on ‎06-20-2025. Is that possible? 

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TiensungA_Altera
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‎06-18-2025 05:55 PM
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TiensungA_Altera_0-1750294372917.png

I would be questioning why emac1 and emac0 clk are disabled for some unknown reason. From the CLK dump from Linux, I believed the Quartus design may have an issue.   

These 2 clock gates the GMAC0 and GMAC1 (emac0_en , emac1_en). That is why GMAC2 is the only one working.  We don't know why yet. 

TiensungA_Altera_1-1750294430887.png

Thanks for all the dumps. 

Can  you send us the file below? We would need to inspect your SOF file. 

XXX.sof  

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K606
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‎06-19-2025 01:10 AM
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Hi @TiensungA_Altera ,

 

In terms of the clocking setup - I am currently doing the following:

 

- Feeding the output 1/2.5G port of MAC-0 to the input 1/2.5G port of MAC-1 

- Feeding a custom 25MHz clock generated in the Fabric to the 10/100M ports of each MAC

 

I notice that in the HPS editor, there are these fields:

K606_0-1750320729630.png

Which is confusing, as it makes me wonder why there is the extra option here (also documented here as not used in 1/2.5G

input  wire        emac0_mac_tx_clk_i_wire,     // not used in 1/2.5 Gbps
When exporting the EMAC interface from Qsys to the top level design.
 
 
However - it is not clear from this error report how the signal should in fact be connected to avoid such an error.
 

I have shared the relevant bitstreams here

Many thanks,

K

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TiensungA_Altera
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‎06-19-2025 11:26 PM
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In response to K606

Thanks, we will have to analyze the SOF you provided to further troubleshoot this problem.

We will revert to you when we have more insights on the issue. thanks again!

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K606
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‎06-23-2025 09:12 AM
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In response to TiensungA_Altera

Hi there @TiensungA_Altera  - just wondering if there was any insight here? And also I would be very interested to know what method you are using to debug the designs using only the bitstreams (if that is ok?)!

 

Kind Regards,
K

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Sparrow_Altera
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‎06-20-2025 02:23 PM
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Hello K606

As you wait for the sof file analysis to come back, you can check the below information that one of my colleague shared

 

For a MAC-to-MAC loopback test, it requires additional logic. The main logic that enables this is:

 

Sparrow_Altera_0-1750454428411.png

fyi, this code above has not gone thru validation, but my colleague has tested the basic functionalities (ping and iperf transfers).

The DTSI is correct.

But additional kernel option (network namespace) needs to be enabled to ensure the data transfer is not virtual. This is because  Linux network stack is pretty intelligent to detect transfer between interfaces on the same host and will attempt SW transfers without going thru MAC.

 

Thanks

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K606
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‎06-21-2025 12:53 AM
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In response to Sparrow_Altera

Thanks @Sparrow_Altera!

 

Would you mind expanding on the 'additional kernel option (network namespace)'? Would it just be a case of adding 

CONFIG_NET_NS=y

To the .config?

I also had a look at the snippet you shared, adapting it to my project as followed:

module dual_emac_interface (
    // EMAC0 Signals
    output wire        emac0_mac_tx_clk_o_wire,     // clock out for tx (not used in 10/100 Mbps)
    input  wire        emac0_mac_tx_clk_i_wire,     // clock in for tx (not used in 1/2.5 Gbps, but fed signal either way - should be 25MHz)
    input  wire        emac0_mac_rx_clk_wire,       // clock for rx path
    output wire        emac0_mac_rst_tx_n_wire,     // reset for tx path
    output wire        emac0_mac_rst_rx_n_wire,     // reset for rx path
    output wire        emac0_mac_txen_wire,         // transmit enable signal
    output wire        emac0_mac_txer_wire,         // transmit error signal
    input  wire        emac0_mac_rxdv_wire,         // receive data valid signal
    input  wire        emac0_mac_rxer_wire,         // receive error signal
    input  wire [7:0]  emac0_mac_rxd_wire,          // for 10/100 Mbps designs, only bits [3:0] are used
    input  wire        emac0_mac_col_wire,          // collision signal (half-duplex only)
    input  wire        emac0_mac_crs_wire,          // carrier sense signal (half-duplex only)
    output wire [2:0]  emac0_mac_speed_wire,        // set to 3'b011 for 1 Gbps (125 MHz)
    output wire [7:0]  emac0_mac_txd_o_wire,        // for 10/100 Mbps designs, only bits [3:0] are used

    // EMAC1 Signals
    output wire        emac1_mac_tx_clk_o_wire,
    input  wire        emac1_mac_tx_clk_i_wire,
    input  wire        emac1_mac_rx_clk_wire,
    output wire        emac1_mac_rst_tx_n_wire,
    output wire        emac1_mac_rst_rx_n_wire,
    output wire        emac1_mac_txen_wire,
    output wire        emac1_mac_txer_wire,
    input  wire        emac1_mac_rxdv_wire,
    input  wire        emac1_mac_rxer_wire,
    input  wire [7:0]  emac1_mac_rxd_wire,
    input  wire        emac1_mac_col_wire,
    input  wire        emac1_mac_crs_wire,
    output wire [2:0]  emac1_mac_speed_wire,
    output wire [7:0]  emac1_mac_txd_o_wire
);

    reg emac0_mac_tx_clk_i_reg, emac0_mac_rxer_reg, emac0_mac_rxdv_reg;
    reg [7:0] emac0_mac_rxd_reg;

    reg emac1_mac_tx_clk_i_reg, emac1_mac_rxer_reg, emac1_mac_rxdv_reg;
    reg [7:0] emac1_mac_rxd_reg;

    assign emac1_mac_tx_clk_i_wire = emac0_mac_tx_clk_o_wire;
    assign emac1_mac_rx_clk_wire = emac0_mac_tx_clk_o_wire;
    assign emac1_mac_rxdv_wire = emac1_mac_rxdv_reg;
    assign emac1_mac_rxer_wire = emac0_mac_txer_wire;
    assign emac1_mac_rxd_wire = emac1_mac_rxd_reg;
    assign emac1_mac_col_wire = 1'b0;
    assign emac1_mac_crs_wire = 1'b1;  
    assign emac1_mac_speed_wire = 3'b011;

    assign emac0_mac_tx_clk_i_wire = emac1_mac_tx_clk_o_wire;
    assign emac0_mac_rx_clk_wire = emac1_mac_tx_clk_o_wire;
    assign emac0_mac_rxdv_wire = emac0_mac_rxdv_reg;
    assign emac0_mac_rxer_wire = emac1_mac_txer_wire;
    assign emac0_mac_rxd_wire = emac0_mac_rxd_reg;
    assign emac0_mac_col_wire = 1'b0;
    assign emac0_mac_crs_wire = 1'b1;  
    assign emac0_mac_speed_wire = 3'b011;

    always @ (posedge emac1_mac_tx_clk_o_wire) begin
        if(!emac1_mac_rst_tx_n_wire) begin
            emac0_mac_rxdv_reg <= 1'b0;
            emac0_mac_rxd_reg <= 8'b0;
        end else begin
            emac0_mac_rxdv_reg <= emac1_mac_txen_wire;
            emac0_mac_rxd_reg <= emac1_mac_txd_o_wire;
        end
    end   

    always @ (posedge emac0_mac_tx_clk_o_wire) begin
        if(!emac0_mac_rst_tx_n_wire) begin
            emac1_mac_rxdv_reg <= 1'b0;
            emac1_mac_rxd_reg <= 8'b0;
        end else begin
            emac1_mac_rxdv_reg <= emac0_mac_txen_wire;
            emac1_mac_rxd_reg <= emac0_mac_txd_o_wire;
        end
    end   
   
endmodule

I again found the same initialisation error as here

With the emac clock tree as followed:

$ cat /sys/kernel/debug/clk/clk_summary | grep emac
root@localhost:~# cat /sys/kernel/debug/clk/clk_summary | grep emac
          emaca_free_clk              1        1        0   250000000          0     0  50000         Y
             emac2_clk                1        1        0   250000000          0     0  50000         Y
             emac1_clk                0        0        0   250000000          0     0  50000         Y
             emac0_clk                0        0        0   250000000          0     0  50000         Y
          emac_ptp_free_clk           1        1        0   400000000          0     0  50000         Y
             emac_ptp_clk             1        1        0   400000000          0     0  50000         Y
                i2c_emac2_pclk        0        0        0   100000000          0     0  50000         Y
                i2c_emac1_pclk        0        0        0   100000000          0     0  50000         Y
                i2c_emac0_pclk        0        0        0   100000000          0     0  50000         Y
          emacb_free_clk              0        0        0    70000000          0     0  50000         Y

Many thanks,
K

In response to Sparrow_Altera
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MattG_Altera
Employee
‎06-21-2025 07:07 AM
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Yes, adding CONFIG_NET_NS=y to .config will enable network namespace functionality in the kernel.

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K606
New Contributor III
‎06-24-2025 07:36 AM
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Solved: bring MAC signals up a module

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