Agilex5 .sof programming error

[K606]

Has anybody ever seen this error when trying to program a design with a .sof:

CPU:   Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A55/A76)
Model: SoCFPGA Agilex5 Terasic Atum A5
DRAM:  2 GiB (effective 4 GiB)
Core:  47 devices, 25 uclasses, devicetree: separate
WDT:   Not starting watchdog@10d00200
WDT:   Not starting watchdog@10d00300
WDT:   Not starting watchdog@10d00400
WDT:   Not starting watchdog@10d00500
WDT:   Not starting watchdog@10d00600
NAND:  0 MiB
MMC:   mmc0@10808000: 0
Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
Loading Environment from UBI... "Synchronous Abort" handler, esr 0x96000010, far 0x108d2000
elr: 0000000080263ce8 lr : 0000000080263ef4 (reloc)
elr: 00000000ffd54ce8 lr : 00000000ffd54ef4
x0 : 00000000108d2000 x1 : 0000000000003228
x2 : 00000000ff8f4d30 x3 : 0000000000003260
x4 : 0000000000004e3c x5 : 0000000000006320
x6 : 0000000000003234 x7 : 0000000000000001
x8 : 00000000ff8e8a70 x9 : 0000000000003228
x10: 00000000ff8e65ec x11: 0000000000000798
x12: 0000000000000000 x13: 00000000ff8e8a70
x14: 00000000ffffffff x15: 00000000ff8e643d
x16: 00000000ffcfdb90 x17: 0000000000000000
x18: 00000000ff8eed90 x19: 00000000ff8f4d30
x20: 00000000ff8f1360 x21: 00000000ff8f12c0
x22: 00000000ff8fb3b0 x23: 0000000000000001
x24: 0000000000000000 x25: 0000000000000000
x26: 0000000000000000 x27: 0000000000000000
x28: 0000000000000000 x29: 00000000ff8e6750

Code: 32000021 d5033fbf b9000001 d65f03c0 (b9400001)
Resetting CPU ...

### ERROR ### Please RESET the board ###

 I am using this build flow for the OS, and the GHRD from CDROM v1.4.0

It is worth noting that when programming with the .jic generated by the same project using:

quartus_pfg -c golden_top_hps.sof golden_top_hps.jic -o device=MT25QU512 -o flash_loader=A5ED065BB32AR0 -o mode=ASX4

There is no such issue.

Thanks

[khtan]

Hi K606,

Sorry for the delay in responding to this thread. Based on the error and your explanation on jic file is working, with the assumption of the same sof file is used for the jic generation as well (not due to mismatch handoff settings), the only difference that I could think of is that the with the sof file, the configuration is volatile/not persistent in FPGA SRAM and lost after every reset or power cycle, thus error will occur when reboot/power cycle and FPGA configuration is not there.

Along these lines

Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1... Loading Environment from UBI... "Synchronous Abort" handler, esr 0x96000010, far 0x108d2000 

1st warning usually non fatal, just indicating cannot load or no sd card

2nd warning is indicating loading environment from NAND/UBI filesystem but fails together with the synchronous abort indicating ARM CPU tries to access the address that is not valid , most likely on the FPGA register side bridges or peripherals

As for JIC , it is stored in persistent memory and loaded automatically every reset/reboot thus HPS is able to boot successfully

Thanks

Regards

Kian