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Arria 10 SoC FPGA Remote update via HPS/linux

GBraj
Beginner
2,601 Views

Hello everybody,

we are using an Intel Arria 10 SX with HPS on a custom board (10AS057K4F40E3SG with Quartus Pro 22.4). The boot flow is as specified on Rocketboards website (https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderCycloneVAndArria10 we modified relevant handoffs files and device trees according to board devices and HPS configurations.

Boot is working: we are using boot from SD, with early I/O release to reduce configuration time, keeping the core rbf and the peripherals rbf in the same .itb file, applying the first in the SPL and the second in uboot.

Now we would like to get a "remote FPGA update" feature without using the partial reconfiguration, having a full FPGA reconfiguration at every reboot. We know that HPS DDR3 relies on FPGA configuration so a full reconfiguration via Linux without reboot is not possible, but reboot is fine for our purposes. Power cycle the board is not.

Which is the best practice to follow? Our idea is to modify via SSH/TFTP the FIT image on the FAT partition (.itb) file and then issue a reboot command via Linux without having a power cycle of the board.

This way seems to not working as intended since at reboot the SPL sees that the FPGA is already configured (but with the old image) and it does not start the FPGA configuration. Is there a way to force it via SPL/uboot?

I hope I made myself clear, otherwise please ask me further details.

Thanks in advance.

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1 Solution
aikeu
Employee
1,986 Views

Hi GBraj,


Double config can solve the some issue related DDR issue in A10. So it will be required.


Thanks.

Regards,

Aik Eu


View solution in original post

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19 Replies
Kenny_Tan
Moderator
2,547 Views

Kindly note that there will be some slowness on the first reply due to the public holiday, we will get back to you as soon as possible.



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aikeu
Employee
2,526 Views

Hi GBraj,


I think you can refer to the option 2 under Reducing Arria 10 Fabric Configuration Time related for loading the FPGA fabric in U-boot:

https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderCycloneVAndArria10


Thanks.

Regards,

Aik Eu


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GBraj
Beginner
2,512 Views

Hi Aik,

I'm using already option 2 of the Bootloader. This is the work flow that I want to obtain:

  1. Cold reset (power on)
  2. SPL loads peripheral rbf
  3. TPL u-Boot loads core rbf
  4. TPL boots to linux
  5. linux transfers a new .itb file to FAT partition
  6. linux issues reboot command
  7. SPL loads NEW peripheral rbf contained in new .itb file
  8. TPL u-Boot loads new core rbf contained in new .itb file
  9. TPL boots to linux

Mostly similar to this topic https://forum.rocketboards.org/t/arria10-u-boot-2021-04-support-reboot-from-linux/2845

The current situation is this:

  1. Cold reset (power on)
  2. SPL loads peripheral rbf
  3. TPL u-Boot loads core rbf
  4. TPL boots to linux
  5. linux transfers a new .itb file to FAT partition
  6. linux issues reboot command
  7. SPL skips peripheral load (BAD, we want the new peripiheral image!)
  8. TPL u-Boot attempts to load core rbf
  9. TPL hangs and watchdog reboots (repeat from step 6).

The problem is that in step 7, SPL skips peripheral load since FPGA is already programmed.

Is there a option to force the peripheral and core programming at every reboot issued by linux, without having a power cycle of the board? I'm trying to use the patch in uboot suggested in that topic but it seems to not work as intended.

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aikeu
Employee
2,488 Views

Hi GBraj,


I will try to consult further regaring the issue that you are facing.


Thanks.

Regards,

Aik Eu


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aikeu
Employee
2,436 Views

Hi GBraj,


When in U-boot, did you try to perform the below before perform reboot in linux kernel?


setenv coreaddr 0x1000000

load mmc 0:1 ${loadaddr} fit_spl_fpga.itb

imxtract ${loadaddr} fpga-core-1 ${coreaddr}

fpga load 0 ${coreaddr} ${filesize}



Thanks.

Regards,

Aik Eu


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GBraj
Beginner
2,413 Views

Hi aik,

I'm using the standard U-boot code from official Intel repository https://github.com/altera-opensource/u-boot-socfpga ,

I've seen in socfpga_common.h that there is a specific script for programming the core https://github.com/altera-opensource/u-boot-socfpga/blob/61ae22e548ebda525d5216d107e45f20eca70537/include/configs/socfpga_common.h#L193-L194

so I the fpga core is correctly loaded. The problem is in force reloading the peripheral bitstream.

Is there a way to force FPGA programming at every reboot? Maybe changing some code in preloader functions here? https://github.com/altera-opensource/u-boot-socfpga/blob/61ae22e548ebda525d5216d107e45f20eca70537/arch/arm/mach-socfpga/spl_a10.c#L114-L150

 

Or maybe it is better to make a step back and perform the full FPGA programming in SPL at every reboot instead in half in SPL and half in TPL?

 

Regards.

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aikeu
Employee
2,349 Views

Hi GBraj,


Probably can try to modify the code to force it to reload FPGA bit stream by taking out the if (is_fpgamgr_user_mode()) condition when spl_board_init().

Anyway just wanto confirm that referring to this document AN 860: Using Intel® Arria® 10 SoC FPGA Early I/O Release, page 9

https://cdrdv2-public.intel.com/667022/an-a10-soc-fpga-early-io-release-683437-667022.pdf

Did you enable the early IO release in your qsys design?


Thanks.

Regards,

Aik Eu


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aikeu
Employee
2,286 Views

Hi GBraj,


May I know any follow up from the previous comment?


Thanks.

Regards,

Aik Eu


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GBraj
Beginner
2,278 Views

Hi Aik,

sorry for the delay: I've checked out the Early I/O Release and the checkboxes are selected both in "device options" of quartus and also in qsys. Let me try a little bit more next week so I will come to you with extensive trials: I will try also to change the code of the preloader.

 

Regards.

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aikeu
Employee
2,242 Views

Hi GBraj,


Do let me know once you got new findings on your side.


Thanks.

Regards,

Aik Eu


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aikeu
Employee
2,197 Views

Hi GBraj,


Any follow up from your side on this week?


Thanks.

Regards,

Aik Eu


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GBraj
Beginner
2,181 Views

Hi Aik,

I've checked again the early I/O release, both in quartus and in qsys. Results are attached. 

quartus_early.pngqsys.png

 

 

 

 

 

 

 

 

 

 

 

 

This is a screenshot of the console during booting, so it seems that early I/O are configured correctly.

uboot.png

 

 

 

 

 

 

 

 

 

 

 

 

 

I've prepared two .its files with two different bistreams (inside every .itb file there is the periph/core .rbf pair) and I confirm that only rebooting the board via linux does not trigger FPGA reconfiguration. Only a power cycle triggers the correct reconfiguration with the new .itb file. Probably the preloader is checking only the flags is_fpgamgr_user_mode and is_fpgamgr_early_user_mode.

So from now I will try to modify the code of spl_a10.c file. Is it correct to modify only the spl_board_init() function or I need to check other files in the preloader?

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aikeu
Employee
2,134 Views

Hi GBraj,


I cannot confirm whether just to modify that file spl_a10.c will be enough as I never did that particular attempt before, it may have some dependencies on the other file. Anyway can try modify first and see the outcome.


Thanks.

Regards,

Aik Eu


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GBraj
Beginner
2,120 Views

Hi aik,

I have some news: I modified the spl_board_init() function in spl_a10.c, changing the following lines (https://github.com/altera-opensource/u-boot-socfpga/blob/61ae22e548ebda525d5216d107e45f20eca70537/arch/arm/mach-socfpga/spl_a10.c#L126-L152)  from that:

	/* If the full FPGA is already loaded, ie.from EPCQ, config fpga pins */
	if (is_fpgamgr_user_mode()) {
		ret = config_pins(gd->fdt_blob, "shared");

		if (ret)
			return;

		ret = config_pins(gd->fdt_blob, "fpga");
		if (ret)
			return;
	} else if (!is_fpgamgr_early_user_mode()) {
		/* Program IOSSM(early IO release) or full FPGA */
		fpgamgr_program(buf, FPGA_BUFSIZ, 0);

		/* Skipping double program for combined RBF */
		if (!is_fpgamgr_user_mode()) {
			/*
			 * Expect FPGA entered early user mode, so
			 * the flag is set to re-program IOSSM
			 */
			force_periph_program(true);

			/* Re-program IOSSM to stabilize IO system */
			fpgamgr_program(buf, FPGA_BUFSIZ, 0);
			force_periph_program(false);
		}
	}

to this:

	/* If the full FPGA is already loaded, force re-program (needed for reboot) */
	if (is_fpgamgr_user_mode()) {
		
		force_periph_program(true);
		fpgamgr_program(buf, FPGA_BUFSIZ, 0);
		fpgamgr_program(buf, FPGA_BUFSIZ, 0);
		force_periph_program(false);

	} else if (!is_fpgamgr_early_user_mode()) {
		/* Program IOSSM(early IO release) or full FPGA */
		fpgamgr_program(buf, FPGA_BUFSIZ, 0);

		/* Skipping double program for combined RBF */
		if (!is_fpgamgr_user_mode()) {
			/*
			 * Expect FPGA entered early user mode, so
			 * the flag is set to re-program IOSSM
			 */
			force_periph_program(true);

			/* Re-program IOSSM to stabilize IO system */
			fpgamgr_program(buf, FPGA_BUFSIZ, 0);
			force_periph_program(false);
		}
	}

So, in the first if I'm checking the FPGA status: since the boot is forced to SD/MMC card in my application, the FPGA can't be already loaded. This will break the compatibility with EPCQ load but in our case is not needed. Then, if it is in user mode, a reboot has been issued, forcing the reprogram. About this, I have a question: is the double programming needed for stability as suggested in the else condition below? Or a single reprogram of the peripherals is enough?

Regards. 

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aikeu
Employee
2,076 Views

Hi GBraj,


It looks like it is programming the same content again fom the code itself...

I do not understand why but anyway does the changes works on your side after linux issues reboot command?


Thanks.

Regards,

Aik Eu


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GBraj
Beginner
2,042 Views

Hi Aik,

 

now the changes are working as intended: a full reprogram (periph+core) of the FPGA is triggered on every reboot command by linux and also with the HPS cold reset button. Probably a more "elegant" solution would be an ifdef clause linked to a certain defconfig during the build stage of U-boot, in order to keep the compatibility with other boot sources (EPCQ/etc)...but it works.

About the double programming of peripherals, I've found some references in the official source code: https://github.com/altera-opensource/u-boot-socfpga/blob/61ae22e548ebda525d5216d107e45f20eca70537/arch/arm/mach-socfpga/misc_arria10.c#L142-L157

Could you please investigate internally with your colleagues if double periph config is needed on Arria 10 SoC?

 

Regards.

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aikeu
Employee
2,013 Views

Hi GBraj,


Sure I will try to check from the team.


Thanks.

Regards,

Aik Eu


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aikeu
Employee
1,987 Views

Hi GBraj,


Double config can solve the some issue related DDR issue in A10. So it will be required.


Thanks.

Regards,

Aik Eu


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aikeu
Employee
1,900 Views

Hi GBraj,


I am closing this thread for now.


p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.


Thanks.

Regards,

Aik Eu


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