Arria10 DDR ECC Initialization

[PHJ]

Do I need to explicitly initialize DDR to known values after enabling ​ECC for the Arria10 DDR ?

The A10 HPS technical reference manual has the following notes against the ECCCTRL1 and ECCCTRL2 registers:

"This bit is used to set the initialize the memory and ecc to a known value"

This would suggest that explicit initialization of each DDR location is not required. Which "bit" is this referring to. There is no description of any initialization operation in either of these registers.​

[EBERLAZARE_I_Intel]

Hi,

Based on my experience, those registers are to left to default values. You do not need to do such after enabling ECC for the Arria 10 DDR.

[EBERLAZARE_I_Intel]

Hi,

Do you have any additional questions?

[PHJ]

​Hi -

I would like to know what the bit referenced in the reference manual is referring to ?  It is in a comment that refers to the whole register.

From my testing I do need to explicitly initialize all of DDR to avoid seeing EEC errors when I first access a location.

Thanks,

Paul

[EBERLAZARE_I_Intel]

Hi Paul,

I apologize for missing out your initial question "Which "bit" is this referring to. There is no description of any initialization operation in either of these registers.​"

The "bit" mentioned in ECCCTRL1, is register 0xFFCFB100

while, the "bit" mentioned in ECCCTRL2, is register 0xFFCFB104

Are you configuring the HPS external memory interface (EMIF) to be 16 bits wide with error checking and correction (ECC) enabled? If so, please refer our Intel® Arria® 10 SX Device Errata and Design Recommendations below:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/es/es-1053.pdf#page=9

Regards.

[PHJ]

​Thanks for the quick response.  We are using DDR in 16-bit mode with ECC enabled and had seen this errata.  We are not seeing adverse system performance in this mode, but would be interested to know more details on this - esp what the "sometimes" from the errata text really means, and how doing all DDR accesses via a copyback cache affects the errata condition.

[EBERLAZARE_I_Intel]

Hi Paul,

I could not find any hard details.

Based on my knowledge, in HPS x16 bit interface with auto-correction enabled, the write performance degrades because there is one extra write-to-read AND read-to-write turnaround time for every write. The degradation will be significant.

I would recommend that you used other mode(x40) if you need the auto-correction feature, if you face the degradation in you system perfomance.

Best Regards.