Intel® SoC FPGA Embedded Development Suite
Support for SoC FPGA Software Development, SoC FPGA HPS Architecture, HPS SoC Boot and Configuration, Operating Systems
Announcements
The Intel sign-in experience has changed to support enhanced security controls. If you sign in, click here for more information.
391 Discussions

Hi, I am trying to use intel's PCIE Avalon MM DMA IP core. Is there a way for me to generate this core outside platform designer? Also is there an example to instantiate this dma engine without using platform designer.

HungLam
Beginner
529 Views

trying to generate & use PCIE (HIP) along with avalon mm DMA IP for arria 10.

0 Kudos
3 Replies
HungLam
Beginner
359 Views

I am currently using the platform designer to generate the IP core and then instantiating it in my top level design.

I was curious to know why only the platform designer ip catalog shows pcie-dma ip.

In the main ip catalog (the one on right hand side of quartus main page) only the PCIE HIP core without dma is available.

BoonT_Intel
Moderator
359 Views

Hi I think this is because Platform manager provide the auto address mapping for the avalon-mm port in PCIe, thus seldom user will need it without the Platform manager.

Yes, I think the only way is to generate the PCIe under platform manager and export the port to your top level.

HungLam
Beginner
359 Views

Ok, thanks for the explanation.

Reply