trying to generate & use PCIE (HIP) along with avalon mm DMA IP for arria 10.
Link Copied
I am currently using the platform designer to generate the IP core and then instantiating it in my top level design.
I was curious to know why only the platform designer ip catalog shows pcie-dma ip.
In the main ip catalog (the one on right hand side of quartus main page) only the PCIE HIP core without dma is available.
Hi I think this is because Platform manager provide the auto address mapping for the avalon-mm port in PCIe, thus seldom user will need it without the Platform manager.
Yes, I think the only way is to generate the PCIe under platform manager and export the port to your top level.
Ok, thanks for the explanation.
For more complete information about compiler optimizations, see our Optimization Notice.