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BSP Editor fails to generate files

MV
New Contributor I
1,053 Views

I am trying to generate preloader for CycloneV SoC using BSP Editor.

I am successfully generating HDL in the Platform Designer and able to compile the design.
However, when running the bsp-editor the attempt fails on missing files which were actually supposed to be generated through bsp-editor and placed to <project_path>\software\spl_bsp\.
The first missing file is "reset_config.h.template".
The only similar file found across the filesystem is 
c:\intelFPGA\20.1\embedded\ip\altera\preloader\src\reset_config.h

```

WARNING: Tcl script "C:\intelfpga\20.1\embedded\ip\altera\preloader\spl_callbacks.tcl spl C:/Users/CurrentUser/Altera/DE10_NANO_SoC/software/spl_bsp" error: couldn't open "reset_config.h.template": no such file or directory

```

The installed tools are 20.1.0.711:
QuartusLiteSetup-20.1.0.711-windows.exe
Intel SoC FPGA Embedded Development Suite Standard Edition

I do not have a space in any of the paths; tried on two different W10 machines.

Is this a bug?

0 Kudos
1 Solution
Rajeshm
Novice
932 Views

Hi @MV ,

I solved this error for me. This is due to Python installed alone with SoC EDS. This python trying to access a package. but that is not available in it . To solve this error, we have to remove this python and download latest python then install it in that same folder. please reply me if it is working for you.

I'm using 

1. Quartus-lite-20.1.0.711-windows 2. SoCEDSSetup-20.1.0.711-windows

 

Steps

1.  go to Folder Path - C:\intelFPGA_lite\20.1\embedded\host_tools\python and remove all the content in side the folder.

2. Download "python-3.9.1-amd64" and install it in the same folder path  C:\intelFPGA_lite\20.1\embedded\host_tools\python

 

 

Thanks 

Rajesh M

 

View solution in original post

12 Replies
MarcoWu
Beginner
1,034 Views

I am facing this problem as well, ...>_<... is there any one can share how to solve this problem?

 

MV
New Contributor I
1,024 Views

Hi Marco,

I spent countless hours and nights pondering around since I posted the question. Tried to follow few writeups and various vintages of Altera/Intel tools. It is frustrating when one just cannot follow instructions and get the expected result, right? One of the issues is that the tools are evolving and the examples come mainly from the time when Cyclone V was a hot new SoC. The chip is still relevant today, don't get me wrong, but there is not as much traffic on this and similar forums as few years back. Frequently you can see someone posting a question and then answering his own question *few months later*. That just helps setting the expectations: Brace yourself and stash enough coffee for the long nights.

I plan to summarize more when I am "out of the woods" but at least a bit of advice for now:
- many issues may be caused by different versions of executables than expected being invoked. (As an example Windows10 (if you are taking that route) has it's own tar and that may break things. Setting PATH is the first step:

export PATH=/bin:$PATH


- Most examples were written ~2 years back and not regression tested. Unless you have a reason do not use latest Intel tools and stick with what was used around the time the example was written. Especially Quartus 20 seems to have added more complexity where you have to download and install ARM DS-5  and CygWin while previous Quartus / SoCEDS combinations took care of that in one download.
Since I went back to Quartus / SoCEDS 18.1 things got significantly better.

- Using Linaro, GNU tools and (kernel) sources as close to what the original author used. Once it builds there is a chance to start upgrading bit-by-bit (if there is a reason).

- Quartus is a Linux application. Altera made it operate well on Windows but under the hood it is a Linux based. However, that need for CygWIN and MinGW makes your setup more fragile. Bite the bullet and get out of the Windows comfort zone. I did another "fresh start" two days ago and it is better now. Just finished building preloader, u-boot , kernel and filesystem (busybox for now )  as per
https://bitlog.it/20170820_building_embedded_linux_for_the_terasic_de10-nano.html
(I found this to be a good example to follow).

At the moment my environment is:
(Windows10) VirtualBOX, Ubuntu18, Quartus / SoCEDS 18.1
Even here you end-up googling and installing missing tools but hopefully you won't be spinning wheels in a mud forever - that was my feeling past month

Good luck.

MarcoWu
Beginner
956 Views

Hi @MV :

Thanks for your suggestion, and I have done all the steps as the web link you mentioned by using pure Linux system(Ubuntu 18.04).

But I do really want to know if there is any method to solve this problem with Quartus 20.1 in Windows10. Because the tool been released officially but can't work.

Best regards

Marco Wu

MV
New Contributor I
951 Views

I understand your frustration way too well. I am still working on something what I expected to be covered by "out of the box example".

However, I suspect that the tool as it is (Quartus 20.1) would work with a project fully configured and set-up for this environment. And that looks like a steep hill to climb.
Intel seems to be less focused on FPGA business than it was back in the Altera days when Altera folks didn't have other distraction from their core business.

Good luck - Martin

Rajeshm
Novice
1,005 Views

Hi,

I'm also facing this error. Can anyone help me to solve this problem. 

 

Thanks 

Rajesh M

MV
New Contributor I
996 Views

Hi @Rajeshm ,

Could you please be more specific?  When I posted the issue I was using latest Quartus and associated tools. Are you in that situation?
As you might have seen from my follow-up rolling back to Quartus 18.1 and going under Linux as a host OS for the toolset on my PC was a reasonable workaround. Typically the driving force for upgrading (Quartus) is when the new version addresses known bugs or when you are forced to do so because you are using new chips which are not supported in older version. If your target is as an example Cyclone V SoC then going for 20.1 doesn't give you benefit but headache (IMHO).

Rajeshm
Novice
981 Views

Hi @MV ,

 I'm using then DE10-Nano kit and using Quartus prime lite 20.1 for FPGA design. Ok, Will try with older version and post the results.

 

Thanks 

Rajesh M

MV
New Contributor I
971 Views

Great. One of my boards is also DE10-nano and I got things compiled under Quartus 18.1.

Martin

Rajeshm
Novice
933 Views

Hi @MV ,

I solved this error for me. This is due to Python installed alone with SoC EDS. This python trying to access a package. but that is not available in it . To solve this error, we have to remove this python and download latest python then install it in that same folder. please reply me if it is working for you.

I'm using 

1. Quartus-lite-20.1.0.711-windows 2. SoCEDSSetup-20.1.0.711-windows

 

Steps

1.  go to Folder Path - C:\intelFPGA_lite\20.1\embedded\host_tools\python and remove all the content in side the folder.

2. Download "python-3.9.1-amd64" and install it in the same folder path  C:\intelFPGA_lite\20.1\embedded\host_tools\python

 

 

Thanks 

Rajesh M

 

View solution in original post

MV
New Contributor I
911 Views

Hi @Rajeshm ,

Thanks for the suggestion. It is worth trying. As soon as I have a moment I will go back to the future (20.1) and soo if this was (one of) my problems. I am happy with 18.1 at the moment so I am not pressured but "out of scientific curiosity" want to close the loop sooner or later.

Are you on windows or Linux?

Thanks M.

MV
New Contributor I
882 Views

Hi @Rajeshm 

Tried - and it DOES WORK!

Thanks you - closing this thread with accepted solution.

Martin

MarcoWu
Beginner
901 Views

Hi @Rajeshm :

Thanks for your suggestion, it's workable to me. ^__^.

Best regards

Marco Wu

Reply