Intel® SoC FPGA Embedded Development Suite
Support for SoC FPGA Software Development, SoC FPGA HPS Architecture, HPS SoC Boot and Configuration, Operating Systems
461 Discussions

Can't debug the spl for cycloneVsoc dev kit

CAlex
New Contributor II
965 Views

Hi,

I followed the insruction on Rocketboards.org hwlib for cycloneVsoc on the environment of Quartus PRIME 18.1, soceds 22.1.

I failed to debug the spl made from my project,here is the error information:

 

Connected to running target Intel SoC FPGA - Cyclone V SoC (Dual Core)
cd "D:\board\cyclone_V_soc\ARM_DS\workspace21.1"
Working directory "D:\board\cyclone_V_soc\ARM_DS\workspace21.1"
set substitute-path "/home/chun/CVAV/cv_soc_devkit_ghrd_2020/software/bootloader/u-boot-socfpga/arch/arm/mach-socfpga/" "D:\board\cyclone_V_soc\cv_soc_devkit_ghrd_2020_v4\cv_soc_devkit_ghrd_2020\software\bootloader\u-boot-socfpga\arch\arm\mach-socfpga\"
set substitute-path "/home/chun/ARMDS/cv_soc_devkit_ghrd_2020/software/bootloader/u-boot-socfpga/arch/arm/mach-socfpga/" "D:\board\cyclone_V_soc\cv_soc_devkit_ghrd_2020_v2\cv_soc_devkit_ghrd_2020\software\bootloader\u-boot-socfpga\arch\arm\mach-socfpga\"
source /v "C:\Program Files\Arm\Development Studio 2021.1\sw\debugger\configdb\Scripts\altera_target_check.py"

No SYSID registers could be found. Has a peripheral description file been supplied?

break -d -p "D:\board\cyclone_V_soc\ARM DS\workspace21.1\Ex_cv_build_v2\Source\Fast_src\cal_ctrl.c":129
WARNING(CMD452-COR167):
! Breakpoint 1 has been pended
! No compilation unit matching "D:/board/cyclone_V_soc/ARM DS/workspace21.1/Ex_cv_build_v2/Source/Fast_src/cal_ctrl.c" was found
condition 1
break-script 1 ""
ignore 1 0
break-stop-on-cores 1
unsilence 1
Breakpoint 1 unsilenced
source /v "D:\board\cyclone_V_soc\cv_soc_devkit_ghrd_2020_v10\cv_soc_devkit_ghrd_2020_v6\cv_soc_devkit_ghrd_2020_v6\software\bootloader\debug-spl.ds"
+stop
Execution stopped in SVC mode at S:0xFFFF2BA4
S:0xFFFF2BA4 B {pc} ; 0xffff2ba4
+wait 5s
+reset
+stop
WARNING(CMD315): Target is not running
+wait 5s
+set trust-ro-sections-for-opcodes off
Target has been reset
Execution stopped in SVC mode due to a breakpoint or watchpoint: S:0x00000000
S:0x00000000 LDR pc,[pc,#24] ; [0x20] = 0xA8
+loadfile $sdir/u-boot-socfpga/spl/u-boot-spl 0x0
Loaded section .text: S:0xFFFF0000 ~ S:0xFFFFAD81 (size 0xAD82)
Loaded section .rodata: S:0xFFFFAD84 ~ S:0xFFFFD5D9 (size 0x2856)
Loaded section .data: S:0xFFFFD5DC ~ S:0xFFFFD643 (size 0x68)
Loaded section .u_boot_list: S:0xFFFFD644 ~ S:0xFFFFDDE7 (size 0x7A4)
Entry point S:0xFFFF0000
+start
Starting target with image D:\board\cyclone_V_soc\cv_soc_devkit_ghrd_2020_v10\cv_soc_devkit_ghrd_2020_v6\cv_soc_devkit_ghrd_2020_v6\software\bootloader\u-boot-socfpga\spl\u-boot-spl
Running from entry point
WARNING(CMD399-COR168):
# in D:\board\cyclone_V_soc\cv_soc_devkit_ghrd_2020_v10\cv_soc_devkit_ghrd_2020_v6\cv_soc_devkit_ghrd_2020_v6\software\bootloader\debug-spl.ds:8 while executing: start
! Failed to start the target
! No function named "main" could be found
WARNING(CMD407): Trying the entry point instead
Execution stopped in SVC mode at S:0xFFFF0000
In boot0.h
Unable to read source file /home/chun/CVAV/cv_soc_devkit_ghrd_2020_v6/software/bootloader/u-boot-socfpga/arch/arm/include/asm/arch/boot0.h
S:0xFFFF0000 10,0 B reset ; 0xFFFF0084
+wait
+restore $sdir/u-boot-socfpga/spl/u-boot-spl.dtb binary &__bss_end
Restoring Binary file D:\board\cyclone_V_soc\cv_soc_devkit_ghrd_2020_v10\cv_soc_devkit_ghrd_2020_v6\cv_soc_devkit_ghrd_2020_v6\software\bootloader\u-boot-socfpga\spl\u-boot-spl.dtb into memory
Restoring section S:0x00000000 to S:0x00000B61 into memory S:0xFFFFDDF8 to S:0xFFFFE959
+tbreak spl_boot_device
Breakpoint 3 at S:0xFFFF0D24
on file spl_gen5.c, line 32
+continue
+wait 60s
ERROR(CMD360):
# in D:\board\cyclone_V_soc\cv_soc_devkit_ghrd_2020_v10\cv_soc_devkit_ghrd_2020_v6\cv_soc_devkit_ghrd_2020_v6\software\bootloader\debug-spl.ds:13 while executing: wait 60s
! Wait for stopped timed out
ERROR(CMD656): The script D:\board\cyclone_V_soc\cv_soc_devkit_ghrd_2020_v10\cv_soc_devkit_ghrd_2020_v6\cv_soc_devkit_ghrd_2020_v6\software\bootloader\debug-spl.ds failed to complete due to an error during execution of the script

0 Kudos
1 Solution
CAlex
New Contributor II
889 Views

Hi,

I solve the problem,

It is duel to the unfunctional of the PLL setting of FPGA.

I ignored the SDC warning caused this problem.

 

Sorry to take your time, please do whatever you need to this thread.

Thank you.

 

View solution in original post

0 Kudos
4 Replies
CAlex
New Contributor II
964 Views

Here is the information from the terminal:


U-Boot SPL 2020.07-08705-g35d7cfb999-dirty (Aug 28 2023 - 15:28:23 +0800)
SDRAM calibration failed.
### ERROR ### Please RESET the board ###

0 Kudos
EBERLAZARE_I_Intel
917 Views

Hi,


I may have seen similar issue before, I will need to do some dig in again. I shall get back to you.


0 Kudos
CAlex
New Contributor II
890 Views

Hi,

I solve the problem,

It is duel to the unfunctional of the PLL setting of FPGA.

I ignored the SDC warning caused this problem.

 

Sorry to take your time, please do whatever you need to this thread.

Thank you.

 

0 Kudos
EBERLAZARE_I_Intel
850 Views

Hi,


Thanks for the update. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.



p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.


0 Kudos
Reply