I have a system where a custom IP in FPGA is connected to HPS SYSTEM . The IP uses Quartus FIFO to continuosly get the DATA. The write side is connected to HPS and read side is connected to custom ip. The data is continuosly read at custom IP side. When the transfer happens(using software) I see that the FIFO is getting empty for certain period before the next transfer happens. I need a continuose transfer whenever its not empty(Unless its full and Data is over) . How can I acheive this ??
I am using the h2f_lw bridge for data transfer . Could this be the problem ?
Typically the h2f lightweight bridge is to perform control and status register accesses to peripherals in the FPGA.
The lightweight HPS-to-FPGA bridge is a fixed 32-bit width connection to the FPGA fabric, since most IP cores implement 32-bit control and status register.
I would recommend you use the h2f bridge for data transfer.
The bridge is intended to be used by masters to perform bursting transfers.
We also have a user guide for DCFIFO user guide here for you reference:
Thankyou for the reply.
I have both bridges conenctd to Pipeling bridge and in turn connected to avalon Bus. How can I find the exact addressing for accessing the IP(Wher I have DCFIFO intantiated )
And does it solve the problem I mentioned about the data transfer in FIFO as I mentioned in the post above. ?
I am unsure what you meant by the connection, are you still using the h2f_lw bridge for the data transfer?
Updated DCFIFO configuration user guide: