Cyclone V SoC freeRTOS DS-5 ERROR(CMD360) when trying to program

[mhos]

Hello,

I'm trying to program a Cyclone V SoC using DS-5 based on the demo application from the freeRTOS site (https://www.freertos.org/RTOS_Altera_SoC_ARM_Cortex-A9.html#build_instructions) and I get the following errors:

Stopping running target Intel SoC FPGA - Cyclone V SoC (Dual Core) on connection
Connected to running target Intel SoC FPGA - Cyclone V SoC (Dual Core)
Execution stopped in SVC mode at S:0xFFFF446C
S:0xFFFF446C B {pc} ; 0xffff446c
cd "D:\UserData\z0045mwh\Documents\DS-5 Workspace"
Working directory "D:\UserData\z0045mwh\Documents\DS-5 Workspace"
Execution stopped in SVC mode at S:0xFFFF446C
S:0xFFFF446C B {pc} ; 0xffff446c
source /v "C:\intelFPGA\18.1\embedded\ds-5\sw\debugger\configdb\Scripts\altera_target_check.py"

No SYSID registers could be found. Has a peripheral description file been supplied?

source /v "D:\UserData\z0045mwh\Documents\DS-5 Workspace\FreeRTOSv10.3.1\FreeRTOS\Demo\CORTEX_A9_Cyclone_V_SoC_DK\preloader.ds"
+stop
WARNING(CMD315): Target is not running
+wait 5s
+reset system
+wait 5s
+loadfile "$sdir/uboot-socfpga/spl/u-boot-spl" 0x0
Loaded section .text: S:0xFFFF0000 ~ S:0xFFFF671B (size 0x671C)
Loaded section .rodata: S:0xFFFF671C ~ S:0xFFFF82E4 (size 0x1BC9)
Loaded section .data: S:0xFFFF82E8 ~ S:0xFFFF91AF (size 0xEC8)
Entry point S:0xFFFF0000
Target has been reset
Execution stopped in SVC mode at S:0xFFFF446C
Unable to read source file D:/SJ/nightly/14.0/200/w64/acds/embedded/examples/hardware/av_soc_devkit_ghrd/software/preloader/uboot-socfpga/common/spl/spl.c
S:0xFFFF446C 56,0 B hang+8 ; 0xFFFF446C
+set semihosting enabled 1
Semihosting server socket created at port 8001
+set debug-from *$entrypoint # Set start-at setting to address of $entrypoint
+start
Reloading program
Starting target with image D:\UserData\z0045mwh\Documents\DS-5 Workspace\FreeRTOSv10.3.1\FreeRTOS\Demo\CORTEX_A9_Cyclone_V_SoC_DK\uboot-socfpga\spl\u-boot-spl
Running from entry point
Execution stopped in SVC mode at S:0xFFFF0000
In start.S
Unable to read source file D:/SJ/nightly/14.0/200/w64/acds/embedded/examples/hardware/av_soc_devkit_ghrd/software/preloader/uboot-socfpga/arch/arm/cpu/armv7/start.S
S:0xFFFF0000 39,0 B reset ; 0xFFFF0070
+delete
All user breakpoints deleted
+tbreak spl_boot_device
Breakpoint 2 at S:0xFFFF110C
on file spl.c, line 70
on file spl.c, line 80
+cont
+wait 60s
ERROR(CMD360):
# in D:\UserData\z0045mwh\Documents\DS-5 Workspace\FreeRTOSv10.3.1\FreeRTOS\Demo\CORTEX_A9_Cyclone_V_SoC_DK\preloader.ds:49 while executing: wait 60s
! Wait for stopped timed out
ERROR(CMD656): The script D:\UserData\z0045mwh\Documents\DS-5 Workspace\FreeRTOSv10.3.1\FreeRTOS\Demo\CORTEX_A9_Cyclone_V_SoC_DK\preloader.ds failed to complete due to an error during execution of the script
loadfile "D:\UserData\z0045mwh\Documents\DS-5 Workspace\FreeRTOSv10.3.1\FreeRTOS\Demo\CORTEX_A9_Cyclone_V_SoC_DK\Debug\RTOSDemo.elf"
ERROR(CMD16-TAD11-NAL22):
! Failed to load "RTOSDemo.elf"
! Failed to write 8 bytes to address S:0x0011B754
! General error on memory or register access.
ERROR(COR118-TAD1-NAL52):
! Unable to determine if stopped for semihosting
! Unable to read from register SPSR_UND
! Cannot attain state requested.
Execution stopped in UND mode at S:0xFFFF0004
Unable to read source file D:/SJ/nightly/14.0/200/w64/acds/embedded/examples/hardware/av_soc_devkit_ghrd/software/preloader/uboot-socfpga/arch/arm/cpu/armv7/start.S
ERROR(CMD256-TAD10-NAL52):
! Unable to display contents at location "S:0xFFFF0004"
! Failed to read 4 bytes from address S:0xFFFF0004
! Cannot attain state requested.
set debug-from main
start
WARNING(CMD399-COR168):
! Failed to start the target
! No function named "main" could be found
WARNING(CMD407): Trying the entry point instead
ERROR(CMD399-CMD27-TAD1-NAL52):
! Failed to start the target
! Failed to set a breakpoint
! Unable to read from register SP
! Cannot attain state requested.
wait
ERROR(TAD1-NAL52):
! Unable to read from register SP
! Cannot attain state requested.
Target Message: Could not determine target state

Any input is greatly appreciated.

[EBERLAZARE_I_Intel]

Hi,

It seems that the project may not have been setup correctly, have you tried running the simple demo in the link?

Did the simple demo works? Have you run any RTOS on any devices before?

[mhos]

Hello, 

The simple demo did not work.  It is not able to start the target with u-boot-spl image and fails due to timeout.  

I have not set up RTOS on any device before.  Any clues as to how to overcome this step would be much appreciated.

[EBERLAZARE_I_Intel]

Hi,

For better understanding of the Cyclone V SoC, you may want to check out its HPS TRM doc and our Rocketboards document on how the U-boot and preloader is generated.

I believe you do not have these files in your "pwd" current working directory which is the original U-boot files which is why your execution was not able to execute. You can see your errors reported missing file. You may check in the Rocketboards on how you git fetch U-boot and have all the files ready.

https://rocketboards.org/foswiki/Documentation/CycloneVSoCGSRD

https://www.intel.com/content/www/us/en/programmable/documentation/sfo1410143707420.html

[MscMechatronics]

I have the same very problem. Would very much appreciate help.

Kind regards,

Filip 

[mhos]

Hi Filip,

Sorry but I still don't have a solution to this.  It's taken a bit of a back seat lately while I work on more pressing issues.  Please let me know if you find a solution.