I'm looking for help debugging my application on a DE10-anno SoC kit. In short, I built an application that moves data back and forth between FPGA and HPS. However, my application stops after two runs because an IP receiving data doesn't seem to accept a counter reset. Unfortunately, I'm not experienced in debugging this kind of hardware/software combination. The design is a part of my Embedded Systems master thesis. I want to avoid spending too much time on debugging and I hope someone can give me some tips on how to approach this.
I added a block diagram of my application. The DMAs, the data generator and data checker are all IPs I put together with the platform designer, starting with a golden system reference design. The data generator outputs data that the first DMA copies to the on-chip RAM connected to the HPS. Telling Linux to reserve main memory seemed quite complicated and the on-chip RAM isn't used by Linux. The second DMA reads what's on the on-chip RAM and sends it to the data checker which counts bits and errors. Additionally, the software measures how long it takes and makes sure everything runs smoothly.
While I have some vague ideas what I could check for errors, I don't have a sophisticated plan for debugging. Additionally, I'm not experienced with the debugging tools included in Quartus. I could look into that but I would like to know first which ones are actually helpful in my case. Besides, I can't guarantee that there is only one bug or that the described problem is related to the data checker or not.
I did not follow these instructions. As mentioned above, I made my own design. Would that guide work for my hardware? I have a DE10-nano SoC while that guide is for a Cyclone 5 Development Kit. The chips are on the same family but is that enough?