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We are seeking for ideas with the following issue we have on Cyclone V.
We have a project in development where adding Altera PIO (and sometimes other MM-slaves) breaks the ability to load ELF into NIOS memory (both DDR and on-chip):
$ nios2-download -g --instance 0 --device 1 --cable USB-Blaster[USB-0] c13_commit_C3.elf
Using cable "USB-Blaster [USB-0]", device 1, instance 0x00
Pausing target processor: not responding.
Resetting and trying again: FAILED
Leaving target processor paused
The NIOS is visible on JTAG chain and the memory map is exactly the same as in the working version.
How can such JTAG download problem be debugged?
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Error Running Nios II Project: Downloading ELF Process failed
Description
If the Nios II processor’s
cpu.data_master
port is not connected to all program memories (memories to which the .elf file is downloaded) the software project fails to run on Nios II hardware.
Failure to connect
cpu.data_master
to all program memories is a design error that the Nios II Software Build Tools (SBT) does not detect.
Workaround/Fix
Connect
cpu.data_master
to all program memories.
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Hi Jesson,
Please make sure you have connected Nios debug reset output back to nios reset input QSYS.
See figure 2 in following document as example:
https://www.altera.com/en_US/pdfs/literature/ug/ug_nios2_flash_programmer.pdf
Best regards,
Isaac.
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Hi Jesson,
Did you solve your issue? Let me know please.
Best regards.
Isaac.
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Yes, we've solved the issue. It was caused by a bug in FPGA design not related to JTAG, the problem with NIOS was only a symptom of another issue.
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Hi,
I am having same issue. Can you brief on how you solved it with NIOS ?
Thank you
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I’m glad that your question has been addressed. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
Isaac_V_intel
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